Browsing by Author "Chuang, Che-Hao"

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Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
(2006)
Chen, Zi-Ping
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Chuang, Che-Hao
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Ker, Ming-Dou
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電機學院
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College of Electrical and Computer Engineering
This paper presents a new tracking circuit design without standby leakage current issue for 2.5V/3.3V tolerant I/O buffer, which is suitable for the I/O cells in the mixed-voltage applications with different driving capabilities. One set of mixed-voltage I/O cell with the new proposed 2.5V/3.3V tolerant I/O buffer circuit has been designed and drawn in a 0.13-mu m salicided CMOS process. The new tracking circuit can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.
Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-mu m CMOS technology
(2006)
Shiu, Yu-Da
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Chuang, Che-Hao
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Ker, Ming-Dou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-mu m salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is filly process compatible to general CMOS process without extra process modification.
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection
(2014-10-01)
Chuang, Che-Hao
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Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel on-chip transient voltage suppressor (TVS) integrated with the silicon-based transceiver IC has been proposed and verified in a 0.8 mu m bipolar CMOS DMOS (BCD) process for IEC 61000-4-2 system-level electrostatic discharge (ESD) protection. The structure of on-chip TVS is a high-voltage dual silicon-controlled rectifier (DSCR) with +/- 16 V of high holding voltage (Vh) under the evaluation of the transmission line pulsing (TLP) system with the pulse width of 100 ns. With the high holding current (Ih) of on-chip TVS, this design can pass +/- 200 mA latch-up testing. Therefore, the on-chip TVS can be safely applied to protect the RS232 transceiver with the signal level of +/- 15 V. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact +/- 12 kV stress without any hardware damages and latch-up issue. Moreover, the proposed RS232 transceiver IC has been verified to well protect the system over the IEC 61000-4-2 contact +/- 20 kV stress (class B) in the notebook applications.
System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips
(2017-09-01)
Chuang, Che-Hao
;
Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8-mu m bipolar process for TVS chips. The I-V curves of the TVS and CAN transceiver chip are evaluated by the transmission line pulsing system with the pulse width of 100 ns. The breakdown voltage of the bi-directional TVS chips and CAN transceiver chip are higher than +/- 80 V compared with the +/- 70 V fault voltage tolerance requirement. The clamping voltage of the TVS device is lower than +/- 130 V to discharge ESD current before the CAN transceiver chip breakdown for effective ESD protection. The design target of parasitic inductance by bonding wires is calculated to meet the clamping voltage requirement. The CAN bus transceiver IC with TVS chips co-packaged has been evaluated to pass the IEC61000-4-2 contact +/- 15-kV stress without any hardware damages and latch-up issues.