Browsing by Author "Chuang, Gene C. H."

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A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A Joint Codebook Design for Beamforming Systems with Transmit Antenna Selection
(2011)
Chen, Yi-Chi
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Tsai, Shang-Ho
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Chuang, Gene C. H.
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電機工程學系
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Department of Electrical and Computer Engineering
This paper proposes a codebook design that considers transmit antenna selection and beamforming simultaneously. Under the same amount of feedback bits, the proposed codebook can reduce the number of RF units more than half while its performance is still maintained closely (within 0.1 dB loss) to the codebook designs that use all transmit antennas. Since RF units are expensive, the proposed codebook can greatly reduce the hardware implementational cost with slight performance degradation. Moreover, we analyze the proposed codebook and derive a lower bound of symbol error rate (SER). The derived SER lower bound generally matches the simulation results. Simulation results show the proposed codebook with around half active transmit antennas performs comparable to the Lloyd codebook design with full active antennas.
A Novel Sub-Nyquist Sampling of Sparse Wideband Signals
(2013)
Lin, Chia-Hua
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Tsai, Shang-Ho
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Chuang, Gene C. H.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We propose a Sub-Nyquist sampling scheme using only one mixer, one filter bank with M subfilters and M low rate ADCs. Compared to the MWC (Modulated Wideband Converter) system in [1], the proposed sampling system has several complexity advantages. First, due to the use of only one mixer, the hardware complexity for analog circuits is significantly reduced. Moreover, the system only needs one PN sequence and thus the search complexity for the best sequence is greatly reduced. The use of the best sequence enables the proposed system to achieve a smaller mean square error (MSE) between the original and the reconstructed signals than that of the MWC system. Simulation results are provided to show the performance superiority of the proposed system in terms of MSE and recovery percentage.
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
(2013-04-01)
Yang, Kai-Jiun
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Tsai, Shang-Ho
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Chuang, Gene C. H.
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-N-s butterflies at each stage, where N-s is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let N-s = 4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm(2). The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.