Browsing by Author "Chuang, HH"

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Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
(2000-12-01)
Chuang, HH
;
Jou, JY
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A delay-optimal technology mapping algorithm is developed on a general model of FPGA with hard-wired nonhomogeneous logic block architectures which is composed of different sizes of look-up tables (LUTs) hard-wired together. This architecture has the advantages of short delay of hard-wired connections and area-efficiency of nun-homogeneous structure. The Xilinx XC4000 is one commercial example, where two 4-LUTs are hard-wired to one 3-LUT. In this paper, we present a two-dimensional labeling approach and a level-2 node cut algorithm to handle the hard-wired feature. The experimental results show that our algorithm generates Favorable results for Xilinx XC4000 CLBs, Over a set of MCNC benchmarks. our algorithm produces results with 17% fewer CLB depth than that of FlowMap in similar CPU time on average, and with 4% fewer CLB depth than that of PDDMAP on average while PDDMAP needs 15 times more CPU time.
On circuit clustering for area/delay tradeoff under capacity and pin constraints
(1998-12-01)
Huang, JD
;
Jou, JY
;
Shen, WZ
;
Chuang, HH
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth-first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, comparing to the existing delay-optimized algorithms, ours achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful on solving the timing-driven circuit clustering problem.
Technology mapping for FPGAs with composite logic block architectures
(1996-10-01)
Chuang, HH
;
Shung, CB
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.
Technology mapping for FPGAs with composite logic block architectures
(1996-10-01)
Chuang, HH
;
Shung, CB
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
A new technology mapping algorithm is developed on a general model of FPGA with composite logic block architectures consisting of different sizes of look-up tables (LUTs) and possibly different logic gates. In additions, the logic blocks may have hard-wired connections and limit accessible fanouts. Xilinx XC4000 is one one example containing LUTs of different sizes and AT&T ORCA is another example containing both LUTs and logic gates. We use a multiple-fanout pattern graph library to model the composite logic block and a premapping technique to generate the subject graph dynamically. A new matching algorithm and a new covering algorithm are also developed for the subject graph covering. The experimental results show that our algorithm is an effective technology mapper for FPGAs with composite logic block architectures, especially for large circuits. Over a set of MCNC benchmarks, our algorithm requires on the average 4.25% few CLBs than PPR, 6.79% fewer CLBs than TEMPT, and 2.79% fewer CLBs than ASYL when used as the XC4000 mapper. Over a set of larger benchmarks, our algorithm outperforms PPR by 13.70%. Very encouraging results were obtained when our algorithm is used as an ORCA mapper, while there was no prior published results.