Browsing by Author "Chuang, Li-Pu"

Now showing 1 - 2 of 2

A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
(2008)
Chang, Ming-Hung
;
Chuang, Li-Pu
;
Chang, I-Ming
;
Hwang, Wei
;
電子工程學系及電子研究所
A 300mV 20MHz-35OMHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 mu W at 40MHz/300mV.
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
(2008)
Chuang, Li-Pu
;
Chang, Ming-Hung
;
Huang, Po-Tsang
;
Kan, Chih-Hao
;
Hwang, Wei
A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE[binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9ps when DLL is operating at 500MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2mW at 1GHz with a 1.2V power supply.