Browsing by Author "Chung, C. -C."

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Apparent Dielectric Constant and Effective Frequency of TDR Measurements: Influencing Factors and Comparison
(2009-08-01)
Chung, C. -C.
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Lin, C. -P.
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土木工程學系
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Department of Civil Engineering
When measuring soil water content by time domain reflectometry (TDR), several methods are available for determining the related apparent dielectric constant (K(a)) from the TDR waveform. Their influencing factors and effective frequencies have not been extensively investigated and results obtained from different methods have not been critically compared. The purpose of this study was to use numerical simulations to systematically investigate the effects of electrical conductivity, cable length, and dielectric dispersion on K(a) and the associated effective frequency. Not only does the dielectric dispersion significantly affect the measured K(a), it also plays an important role in how K(a) is affected by the electrical conductivity and cable length. Three methods for determining K(a) were compared, including the dual tangent, single tangent, and derivative methods. Their effective frequencies were carefully examined with emphasis on whether the effects of electrical conductivity, cable length, and dielectric dispersion can be accounted for by the estimated effective frequency. The results show that there is no consistent trend between the change in K(a) and the change in effective frequency as the influencing factors vary. Compensating the effects of electrical conductivity, cable length, and dielectric dispersion by the effective frequency seems theoretically infeasible. To improve the accuracy of TDR soil water content measurements in the face of these influencing factors, future studies are recommended toward TDR dielectric spectroscopy or developing signal processing techniques for determining the dielectric permitivity near the optimal frequency range.
Clarification and calibration of reflection coefficient for electrical conductivity measurement by time domain reflectometry
(2008-07-01)
Lin, C. -P.
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Chung, C. -C.
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Huisman, J. A.
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Tang, S. -H.
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土木工程學系
Measurement of electrical conductivity by time domain reflectometry (TDR) requires knowledge of the source step voltage, which is often implicitly accounted for in the measured reflection coefficient. Errors may arise, however, from imperfect amplitude calibration when transforming the voltage signal into the reflection coefficient signal. This instrument error was identified as a considerable source of error in addition to cable resistance for TDR electrical conductivity measurements. The effect of the instrument error due to imperfect amplitude calibration was theoretically examined by the direct current circuit model and experimentally verified. The instrument error resulted in an overestimation of electrical conductivity while the cable resistance led to an underestimation. We clarified that the series resistors model for correction of cable resistance is accurate if the measured reflection coefficient is corrected for the instrument error. A calibration (correction) method for the measured reflection coefficient was proposed to account for both the instrument error and the effect of cable resistance, leading to a simple, accurate, and theoretically sound procedure for TDR electrical conductivity measurements.
Ultra-low voltage implicit multiplexed differential flip-flop with enhanced noise immunity
(2012-11-08)
Sung, W. -H.
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Lee, M. -C.
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Chung, C. -C.
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Lee, C. -Y.
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電子工程學系及電子研究所
An ultra-low voltage 22T implicit multiplexed differential (IMD) flip-flop (FF) is proposed. An implicit multiplexer is designed to simplify the differential FF complexity, while its control data path is able to enhance the FF noise immunity as well. So, the fully static IMD-FF with modified differential topology provides a sufficient noise margin under voltage scaling. On the other hand, the IMD-FF operation avoids considerable DC current dissipation to save active power and suppresses the idle leakage by stacked transistors. The post-layout simulation in 90 nm CMOS process with 400 mV supply voltage shows that the IMD-FF achieves 56% active power and 42.2% leakage power reduction. The tolerable noise energy is enhanced by 18.9% on average. Finally, this work provides 93% function yield rate under the effect of process-voltage-temperature variations and 40 pJ input noise energy.
Wide duty cycle range synchronous mirror delay designs
(2010-03-04)
Sheng, D.
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Chung, C. -C.
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Lee, C. -Y.
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電機工程學系
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Department of Electrical and Computer Engineering
A wide duty cycle range and small static phase error synchronous mirror delay (SMD) for system-on-chip (SoC) applications is presented. The conventional SMD accepts only the pulsed clock signal and has large static phase error. The proposed SMD uses the edge-trigger mirror delay cell to enlarge the input duty cycle range and the blocking edge-trigger scheme to ensure functionality and performance. Moreover, phase error can be reduced by the proposed delay-matching structure and fine-tuning delay line with a high-resolution delay cell. Simulation results of SMD show that the input clock duty cycle range is from 20 to 80% and the worst static phase error under different process, voltage, and temperature conditions can achieve 18 ps at 400 MHz.