Browsing by Author "Chung, CC"

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A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
(2006-06-01)
Chen, PL
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Chung, CC
;
Yang, JN
;
Lee, CY
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電子工程學系及電子研究所
This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-mu m CMOS process with core area of 0.16 mm(2). Power consumption is 15 mW.@ 378 MHz with 1.8-V supply voltage.
A COMM baseband processor with robust synchronization for high-speed WLAN applications
(2004)
Liu, HY
;
Yu, YH
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Lin, CC
;
Chung, CC
;
Hsu, TY
in this paper, a high-performance and low-cost COFDM baseband processor is presented. With algorithm exploration in channel estimation and phase error tracking, synchronization becomes more robust to enhance system performance. And better design SNR (1.35similar to7.16 dB) can be achieved compared to current solutions. Moreover through architectural exploration, the proposed baseband processor designed in 0.18 um CMOS process contains only 370 K logic gates and 3.3 K byte memory. Measurement results show that better hardware efficiency and performance enhancement is achieved for high-speed WLAN applications.
A new DLL-based approach for all-digital multiphase clock generation
(2004-03-01)
Chung, CC
;
Lee, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new DLL-based approach for all-digital multiphase clock generation is presented. By-using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital. communication applications.
A novel digitally-controlled varactor for portable delay cell design
(2004-12-01)
Chen, PL
;
Chung, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a novel digitally-controlled varactor (DCV) for portable delay cell design is presented. The proposed varactor uses the gate capacitance differences of NAND/NOR gates under different digital control inputs to build up a digitally-controlled varactor. Then the proposed varactor is applied to design a high resolution delay cell and to achieve a fine delay resolution. Different types of NAND/NOR gates (2-input or 3input) for DCV design are also investigated in this paper. The proposed DCV can be implemented with standard cells, thus it can be easily ported to different processes in a short time. A test chip fabricated on a standard 0.35 mum CMOS 2P4M process proves that the proposed delay cell has a fine delay resolution about 1.55 ps. As a result, the proposed DCV exhibits finer resolution, better linearity, and better portability than traditional delay elements, and is very suitable for portable delay cell design.
A portable digitally controlled oscillator using novel varactors
(2005-05-01)
Chen, PL
;
Chung, CC
;
Lee, CY
;
電子物理學系
;
Department of Electrophysics
This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-mu m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.
An all-digital phase-locked loop for high-speed clock generation
(2003-02-01)
Chung, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this brief. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-mum one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P-k-P-k jitter of the output clock is < 70 ps; and the root-mean-square jitter of the output clock is < 22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented in this brief. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications
(2005)
Chen, PL
;
Chung, CC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 x 255). The proposed architecture involves a minimum of hardware and improves jitter performance to reduce the noise and jitter associated with input reference. The dynamic phase averaging (DPA) loop control employing digital phase estimators (DPE) enhances frequency detection resolution and loop stability. A (Q.R) vector counter and an additional state counter serve as phase estimators. The proposed ADPLL includes cascaded DPA loops: the first stage is low frequency loop and the second stage is high frequency loop. A proto-type chip has been implemented with 0.18 mu m 1P6M CMOS process that can operate from 2MHz to 500MHz. The input frequency ranges from 5KHz to 50MHz. Thus it not only reduces the cost and design complexity of ADPLL, but also offers particular advantages for wide multiplication range applications.
Highly selective GaAs/Al0.2Ga0.8As wet etch process for the gate recess of low-voltage-power pseudomorphic high-electron-mobility transistor
(2000-08-01)
Chang, HC
;
Chang, EY
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Chung, CC
;
Kuo, CT
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材料科學與工程學系
A selective wet etch process for the gate recess of the GaAs power pseudomorphic high-electron-mobility transistors (pHEMT's) was developed. The power pHEMT's used in this study were epitaxially grown power Al0.2Ga0.8As/In0.2Ga0.8As pHEMT's with a 250 Angstrom GaAs cap layer and a 300 Angstrom Al0.2Ga0.8As electron-donating layer. The electron-donating layer was used as the etch-stop layer for the gate recess. A selectivity of 3400 : 1 was achieved for GaAs/Al0.2Ga0.8As layers using citric acid/tripotassium citrate/hydrogen peroxide etching solutions in this study. This is the highest selectivity for GaAs/AlxGa1-xAs selective etching reported so far. The pHEMT's processed using this selective etching demonstrated good device power performance, and the wet recess process did not cause any contamination or damage to the device. The test data indicates that this selective etch process can be of practical use for forming the gate recess of the power pHEMT's with good device performance and excellent electrical uniformity.