Browsing by Author "Chung, Chris Chun-Chih"

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Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors
(2019-01-01)
Chung, Chris Chun-Chih
;
Ko, Chun-Ming
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400900 s). Subthreshold characteristics are improved and I_off is drastically reduced (two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve I_on. Surprisingly, after silicidation, both I_on and ${\boldsymbol{\mu }} _{\mathrm{ FE}}$ shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.
Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit
(2018-02-01)
Chung, Chris Chun-Chih
;
Shen, Chiuan-Huei
;
Lin, Jer-Yi
;
Chin, Chun-Chieh
;
Chao, Tien-Sheng
We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high-k metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.