Browsing by Author "Chung, Chun-Chih"

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Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
(2020-02-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
(2019-01-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
We have experimentally demonstrated fully suspended nanowire ( NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm x 12.5-nm); they exhibit a remarkable I-on-I-off ratio of over 10(10). This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S.(min) of 39.22 mV/decade. A ZrO2 seed-layer is inserted under Hf Zr1-x O-x (HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (I-G) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
(2019-11-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm(2) and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I-on-I-off ratio of more than 10(8). We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage ( ${V}_{\textit {TH}}$ ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase ( ${o}$ -phase) before further post-metal annealing (PMA).
Investigation of Hot Carrier Reliability of Ultrathin Poly-Si Nanobelt Junctionless (UTNB-JL) Transistors on Different Underlying Insulators
(2016)
Chang, Jen-Hong
;
Chung, Chun-Chih
;
Lin, Jer-Yi
;
Chao, Tien-Sheng
;
電子物理學系
In this work, we investigate the hot carrier stress (HCS) of ultrathin poly-Si nanobelt junctionless transistors on different insulator (TEOS and Si3N4). Time exponent n suggests the oxide trap charge is the dominant mechanism. The subthreshold slope (S.S.) is improved by acceptor-like interface states generated after HCS, and different S.S. improvement between JL_O and JL_N is caused by surface roughness of channel films resulting from nucleation during channel deposition in LPCVD step.
Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity
(2018-04-01)
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
;
Lee, Sen-Yang
;
Chao, Tien-Sheng
In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility mu FE compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high I-ON/I-OFF current ratio of 1.1 x 10(7). The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an I-ON/I-OFF current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for futuremonolithic 3D integrated-circuit applications.
Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations
(2018-09-01)
Lin, Jer-Yi
;
Tsai, Chan-Yi
;
Shen, Chiuan-Huei
;
Chung, Chun-Chih
;
Kumar, Malkundi Puttaveerappa Vijay
In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n(+) active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a "variable" channel, in which the conduction thickness is thinner or thicker than the physical n(+) thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of I-ON, V-T, S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (I-ON/S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record I-ON , which makes it as a promising device for 3-D integrated nanoelectronics.