Browsing by Author "Chung, Chung-Ping"

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A run-time reconfigurable fabric for 3D texture filtering
(2007)
Wang, Wei-Ting
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Chen, Yi-Chi
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
To reduce area of texture filter for real-time rendering is challenging as user demand for 3-D scene realism increases. This work presents a low-area run-time reconfigurable texture filter design given certain performance requirement A texture filter is a part of a texture unit. The reconfiguration is on a number of bilinear filters as basic function blocks, can be implemented within individual texture unit or across multiple texture units, and is based on hierarchical decomposition of all lands of filtering algorithms. Two reconfiguration designs are proposed and examined The self-content design, in which a texture unit must be equipped with all necessary hardware to deal with all different filtering algorithms; and the sharable design, in which texture units can share their texture filters (and the total amount of useable texture units may thus change). Experimental results show that the sharable design achieves a 12% area reduction, as compared with the self-content design
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration
(2011-09-01)
Wu, I-Wei
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Chung, Chung-Ping
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE_HW). Obviously, since ISE_HW increases the production cost of a processor core, minimizing the area size of ISE_HW becomes important for ISE exploration. On the other hand, because of different requirements in space and speed, ISE_HW usually has multiple hardware implementation options. Under pipeline-stage timing constrain:, some of these options may have the same performance improvement but entail different hardware costs. According to this phenomenon, the area size of ISE_HW can be reduced by performing hardware design space exploration of ISE_HW. Therefore, in this paper, we propose an ISE exploration algorithm that explores not only ISE but also the hardware design space of ISE_HW. Compared with the previous research, our approach resulted in significant improvement in area efficiency and the execution performance.
Early Load: Hiding Load Latency in Deep Pipeline Processor
(2008)
Chang, Shun-Chieh
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Li, Walter Yuan-Hwa
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Kuo, Yuan-Jung
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Chung, Chung-Ping
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資訊工程學系
Load instructions usually have long execution latency in a deep processor pipeline, and have significant impact on overall performance. Therefore, how to hide the load latency becomes a serious problem in processor design. The latency of memory load can be separated into two parts: cache-miss latency and load-to-use latency. Previous work which tried to hide the load latency in a deep processor pipeline has some limitations. In this paper, we propose a hardware-based method, called early load, to hide the load-to-use latency with little hardware overhead. Early load scheme allows load instructions to load data from the cache system before it enters the execution stage. In the meantime, a detection method makes sure the correctness of the early operation before the load instruction enters the execution stage. Our experimental results showed that our approach can achieve 11.64% performance improvement in Dhrystone benchmark and 4.97% in average for MiBench benchmark suite.
ETAHM: An energy-aware task allocation algorithm for heterogeneous multiprocessor
(2008)
Chang, Po-Chun
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Wu, I-Wei
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Shann, Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
In demand of more computing power and less energy use, multiprocessor with power management facility emerges in embedded system design recently. Dynamic Voltage Scaling is such a facility that varies clock speed and supply voltage to save more energy. In this paper, we propose ETAHM to allocate tasks on a target multiprocessor system. In pursuit of global optimal solution, it mixes task scheduling, mapping and DVS utilization in one phase and couples ant colony optimization algorithm. Extensive experiments show ETAHM could save 22.71% more energy than CASPER [1], a state-of-the-art integrated framework that tackles the identical problem with genetic algorithm instead.
Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering
(2014-07-01)
Weng, Tsung-Hsi
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
In the H.264 video compression standard, the deblocking filtering contributes about one-third of all computation in the decoder. With many-core architectures becoming the future trend of system design, computation time can be reduced if the deblocking appropriately apportions its operations to multiple processing elements. In this study, we used a four-pixel-long boundary as the basis for analyzing and exploiting possible parallelism. Compared with the two-dimensional (2D) wavefront method order for deblocking both 1920 x 1080- and 1080 x 1920-pixel frames, the proposed design exhibits speedups of 1.92 and 2.44 times, respectively, given an unlimited number of processing elements. Compared with our previous design, it gains speedups of 1.25 and 1.13 times, respectively. In addition, as the frame size grows, this approach requires only extra time that is proportional to the square root of the frame size increase (keeping the same width to height ratio), pushing the boundary of practical real-time deblocking of increasingly larger video sizes. (C) 2013 Elsevier B.V. All rights reserved.
Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering
(2011)
Weng, Tsung-Hsi
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Wang, Yi-Ting
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
In the H.264 video compression standard, the deblocking filter contributes about one-third of all computation in the decoder. With multiprocessor architectures becoming the future trend of system design, computation time reduction can be achieved if the deblocking filter well apportions its operations to multiple processing elements. In this paper, we apply a 16 pixel long boundary, the basic unit for deblocking in the H.264 standard, as the basis for analyzing and exploiting possible parallelism in deblocking filtering. Compared with existing approaches using a macroblock as a basic unit for analysis, a 16 pixel long boundary by having a finer granularity can improve the chances of increasing the degree of parallelism. Moreover, a possible compromise to fully utilize limited hardware resources and hardware architectural requirements for deblocking are also proposed in this paper. Compared with the 2D wave-front method order for deblocking both 1920*1080 and 1080*1920 pixel sized frames, the proposed design gains speedups of 1.57 and 2.15 times given an un-limited number of processing elements respectively. Using this approach, the execution time of the deblocking filter is proportional to the square root of the growth of the frame size (keeping the same width/height ratio), pushing the boundary of practical real-time deblocking of increasingly larger video sizes.
Extended Instruction Exploration for Multiple-Issue Architectures
(2014-11-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Hsu, Wei-Chung
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Chung, Chung-Ping
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交大名義發表
In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for architectural enhancement, while issuing multiple instructions is a common approach for microarchitectural enhancement. The impact of combining both of these approaches in the same design is not well understood. While previous studies have shown that EI can potentially improve performance in some applications on certain multiple-issue architectures, the algorithms used to identify EI for multiple-issue architectures yield only limited performance improvement. This is because not all arithmetic operations are suited for EI for multiple-issue architectures. To explore the full potential of EI for multiple-issue architectures, two important factors need to be considered: (1) the execution performance of an application is dominated by critical (located on the critical path) and highly resource-contentious (i.e., having a high probability of being delayed during execution due to hardware resource limitations) operations, and (2) an operation may become critical and/or highly resource contentious after some operations are added to the EI. This article presents an EI exploration algorithm for multiple-issue architectures that focuses on these two factors. Simulation results show that the proposed algorithm outperforms previously published algorithms.
Filtering of unnecessary branch predictor lookups for low-power processor architecture
(2008-07-01)
Chiao, Wei-Hau
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
Efforts to reduce power consumption of processors have gained much attention recently. Dynamic branch predictor, including BTB, is exercised in every instruction cycle, yet branch instructions only constitute a small percentage of instructions during program execution. This study proposes a novel method to collect the next branch distances of the recent branch instructions at runtime, in order to eliminate unnecessary branch predictor lookups. Simulation results show that the proposed design reduces the energy consumption in the dynamic branch predictor by an average of 56.95% without performance degradation. The proposed method is fully compatible with BPP and SEPAS, and saves more energy than PPD, Lazy BTB, and EIB does.
iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability
(2008)
Yang, Hui-Chin
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Wang, Li-Ming
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
Goals of this research are to reduce 1. Instruction address bus traffic, 2. Bus power, and 3. Latency, in instruction fetches in a computer system. We propose to move dynamic branch handler from the CPU side to the instruction memory side, and let it be able to autonomously access instructions for CPU CPU needs only to manage the branch handler. Key to success is that the traffic between CPU and dynamic branch handler, with only minor but innovative design changes, can be jar less than that between CPU and instruction memory. The branch handler should hence be capable of PC+4, identifying branches, and tat-get address calculation. We further suggest that even a return stack can easily be incorporated. Simulation using MiBench shows that our theory yields promising results: about 99.98% instruction address traffic and 91.87% related bus bit toggles are reduced.
Instruction set extension exploration in multiple-issue architecture
(2008)
Wu, I-Wei
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Chen, Zhi-Yuan
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Shann, Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement. This is because most algorithms overlook two important considerations: (1) only packing the operations lying on the critical path into ISE can improve performance; (2) the critical path usually changes after packing operations into an ISE. With these considerations, this paper presents an algorithm for ISE exploration based on list scheduling and Ant Colony Optimization (ACO), in which combines ISE exploration and the critical path identification (i.e. instruction scheduling). Results indicate that our approach outperforms the previous work in both performance improvement and area efficiency.
Instruction set extension generation with considering physical constraints
(2007)
Wu, I-Wei
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Huang, Shih-Chia
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Chung, Chung-Ping
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Shann, Jyh-Jiun
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資訊工程學系
In this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.
Load and storage balanced posting file partitioning for parallel information retrieval
(2011-05-01)
Ma, Yung-Cheng
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Chung, Chung-Ping
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Chen, Tien-Fu
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資訊工程學系
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Department of Computer Science
Many recent major search engines on Internet use a large-scale cluster to store a large database and cope with high query arrival rate. To design a large scale parallel information retrieval system, both performance and storage cost has to be taken into integrated consideration. Moreover, a quantitative method to design the cluster in systematical way is required. This paper proposes posting file partitioning algorithm for these requirements. The partitioning follows the partition-by-document-ID principle to eliminate communication overhead. The kernel of the partitioning is a data allocation algorithm to allocate variable-sized data items for both load and storage balancing. The data allocation algorithm is proven to satisfy a load balancing constraint with asymptotical 1-optimal storage cost. A probability model is established such that query processing throughput can be calculated from keyword popularities and data allocation result. With these results, we show a quantitative method to design a cluster systematically. This research provides a systematical approach to large-scale information retrieval system design. This approach has the following features: (1) the differences to ideal load balancing and storage balancing are negligible in real-world application. (2) Both load balancing and storage balancing can be taken into integrated consideration without conflicting. (3) The data allocation algorithm is capable to deal with data items of variable-sizes and variable loads. An algorithm having all these features together is never achieved before and is the key factor for achieving load and storage balanced workstation cluster in a real-world environment. (C) 2011 Elsevier Inc. All rights reserved.
Mechanism for Return Stack and Branch History Corrections under Misprediction in Deep Pipeline Design
(2008)
Chiu, Guan-Ying
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Yang, Hui-Chin
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Li, Walter Yuan-Hwa
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Chung, Chung-Ping
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資訊工程學系
Return stack may be popped due to branch misprediction, corrupting its contents. Meanwhile, erroneous branch history is also recorded for upcoming branch predictions. These errors are more likely in deep pipelines, and their handling affects performance seriously. We study these issues, and propose solutions with two virtues: low hardware overhead, and high branch prediction accuracy comparable with that of a shallow pipeline design. To deal with return stack corruption, any push and pop after any mispredicted branch should be counted and recorded. These simple rules get overly complicated when multiple unresolved branches exist, and anyone may be erroneous, as is common in deeper pipelines. Next, to deal with branch history contamination, extra history bits, plus a branch confirmation pointer are needed. The experiment result shows that our design is effective, about 4%similar to 9% performance improvement in MiBench.
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
(2015-07-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
Next-generation digital entertainment and mobile communication devices are anticipated to require greater processor performance. To meet these demands, several researchers have attached a reconfigurable hardware accelerator to the base processor core. The reconfigurable hardware accelerator, termed a reconfigurable customized functional unit (RCFU), is usually realized by multiple processing elements (PE) organized in matrix form. The structure of the RCFU is generated from hot operation patterns of specific applications. Other than the RCFU, \'multiple-issue\' is another microarchitectural technique to increase the performance. However, the impact of combining both of these approaches in the same design is not yet well understood. This problem motivates us to design RCFU generation and exploitation algorithms for a multiple-issue processor. To allow more operations to execute on the RCFU simultaneously, the proposed generation algorithm merges several data-independent operation patterns to construct the RCFU architecture. To schedule operations on both the RCFU and functional units (FU) of the base processor core simultaneously, the proposed exploitation algorithm presents a model to represent all available computing resources from both the FUs of the base processor and the PEs in the RCFU. Using this model, the RCFU exploitation problem can be considered as an instruction-scheduling problem. Our experiment achieves an average improvement in execution performance of 50% compared with previous efforts [2, 5].
Run-time reconfiguration scheduling of 3D-rendering on a reconfigurable system
(2005)
Chiang, Kuen-Cheng
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Lee, Meng-Tho
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
With the dramatically increasing demands for multimedia processing capabilities in portable electronic devices, the architectural supports for various multimedia computations in one platform are crucial to the success of a product. Although application-specific accelerators have performance advantages, their inflexibilities seriously impede the applicability and shorten product lifetime. On the other hand, a general-purpose processor has benefits to wide applicability but can not meet the real-time criteria in many cases. Therefore, we develop a platform consisting of a general-purpose CPU, an array of processing elements, and a shared memory to transfer data between them. In addition, we propose two scheduling methods, First-Come-First-Serve and Priority, to process the 3D models with a better performance. Experimental results indicate that the priority scheduling significantly improves the 3D-rendering in both computation speed and silicon area, compared with FCFS scheduling. Given the same speed requirements on both FCFS and priority scheduling methods, the priority scheduling requires only 75% of the silicon area. On the other hand, it yields 30% to 80% speedup with the same area. Moreover, with priority scheduling, its performance advantage can be further increased by skills such as partial reconfiguration and multi-context configuration, to reduce its reconfiguration overhead.
Set Utilization Based Dynamic Shared Cache Partitioning
(2011)
Deayton, Peter
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
As the number of processors sharing a cache increases, conflict misses due to interference amongst competing processes have an increasing impact on the individual performance of processes. Cache partitioning is a method of allocating a cache between concurrently executing processes in order to counteract the effects of inter-process conflicts. However, cache partitioning methods commonly divide a shared cache into private partitions dedicated to a single processor, which can lead to underutilized portions of the cache when set accesses are non-uniform. Our proposed method compliments these cache partitioning algorithms by creating an additional shared partition able to be shared amongst all processors. Underutilized areas of the cache are identified by a monitoring circuit and used for the shared partition. Detection of underutilization is based on the number of unique set accesses for a given allocated way. For a 16-way set associative cache, the implementation of our method requires 64 bytes of storage overhead per core in addition to that needed for the method that determines the sizes of the private partitions. For the tested system, our method is able to improve performance over the traditional LRU policy for a number of selected benchmark sets by an average of 1.4% and up to 13.3% for a two core system and an average of 1.4% and up to 7.8% for a four core system, and is able to improve the performance of a conventional cache partitioning method (Utility-Based Cache Partitioning) by an average of 0.1% and up to 0.5% for both a two and four core systems.
Smaller split L-1 data caches for multi-core processing systems
(2009)
Adamo, Oluwayomi
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Naz, Afrin
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Janjusic, Tommy
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Kavi, Krishna
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Chung, Chung-Ping
As more cores (processing elements) are included in a single chip, it is likely that the sizes of per core L-1 caches will become smaller while more cores will share L-2 cache resources. It becomes more critical to improve the use of L-1 caches and minimize sharing conflicts for L-2 caches. In our prior work we have shown that using smaller but separate L-1 array data and L-1 scalar data cache, instead of a larger single L-1 data cache, can lead to significant performance improvements. In this paper we will extend our experiments by varying cache design parameters including block size, associativity and number of sets for L-I array and L-1 scalar caches. We will also present the affect of separate array and scalar caches on the non-uniform accesses to different (L-1) cache sets exhibited while using a single (L-1) data cache. For this purpose we use third and fourth central moments (skewness and kurtosis), which characterize the access patterns. Our experiments show that for several embedded benchmarks (from MiBench) split data caches significantly mitigate the problem of non-uniform accesses to cache sets (leading to more uniform utilization of cache resources, reduction of conflicts to cache sets, and minimizing hot spots in cache). They also show that neither higher set-associativities nor large block sizes are necessary with split cache organizations.