Browsing by Author "Chung, Jen-Feng"

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Anticipatory access pipeline design for phased cache
(2008)
Hsueh, Chih-Wen
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Chung, Jen-Feng
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Van, Lan-Da
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Lin, Chin-Teng
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電控工程研究所
For an embedded processor, the cache design almost occupies half chip area and power consumption. According to Amdahl's law, if the power consumption of cache memories is reduced, the embedded processor can significantly save much power. However, the cache misses result in the penalty of thousands of cycles waiting and power consumption due to increasing the number of external memory access. Based on the above reason, the phased cache design is proposed and can largely improve the power consumption which wastes a set-associative cache. In this paper, the embedded pipelining processor without stalling and low-power phase cache is practiced with high-level simulation to achieve high-performance and low-power design. As experimental results, the proposed phase cache can reduce 44% power consumption compared with traditional one-access-cycle cache and eliminate pipeline stalls incurred by phased cache with only 6% gate count overhead.
Bio-inspired 0.35 mu m CMOS Time-to-Digital Converter with 29.3ps LSB
(2006)
Mozsary, Andras
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Rodriguez-Vazquez, Angel
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Chung, Jen-Feng
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Roska, Tamas
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電控工程研究所
Time-to-Digital Converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in Barn Owl. The circuit occupies small silicon area, and its direct mapping from time to position-code makes conversion rates up to 500Msps possible. Specialty of the circuit is the structural and functional symmetry. Therefore the role of START and STOP signals are interchangeable. In other words negative delay is acceptable: The circuit has no dead time problems. These are benefits of the biology model of the auditory scene representation in the bird\'s brain. The prototype chip is implemented in 0.35 mu m CMOS having less than 30ps single-shot resolution in the measurements.
CNN-based local motion estimation chip for image stabilization processing
(2006)
Lin, Chin-Teng
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Chen, Shi-An
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Cheng, Ying-Chang
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Chung, Jen-Feng
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電控工程研究所
This paper is to investigate a novel design for local motion vectors (LMVs) of image sequences, which are often used in a digital image stabilization (IS) system. The IS technique removes unwanted shaking phenomenon in image sequences captured by hand-held camcorders. It includes two main parts such. as motion estimation and compensation. Most of computation power occurs in the part of motion estimation. In order to reduce this complexity, an idea, which integrates an adaptive-threshold method and cellular neural networks (CNN) architecture, is designed to improve this problem. The design only implements the most important local motion estimation with the array size of 19x25 pixels. Experimental results with HSPICE simulation and CNNUM are shown that the proposed architecture fast searches the location of possible LVMs and has the capability of real-time operations. The complete design has integrated into the total area of 8.1mm(2) by using TSMC 0.35 mu m mixed-signal process.
FPGA Implementation of 4-Channel ICA for On-line EEG Signal Separation
(2008)
Huang, Wei-Chung
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Hung, Shao-Hang
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Chung, Jen-Feng
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Chang, Meng-Hsiu
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Van, Lan-Da
Blind source separation of independent sources from their mixtures is a common problem for multi-sensor applications in real world, for example, speech or biomedical signal processing. This paper presents an independent component analysis (ICA) method with information maximization (Infomax) update applied into 4-channel one-line EEG signal separation. This can be implemented on FPGA with a fixed-point number representation, and then the separated signals are transmitted via Bluetooth. As experimental results, the proposed design is faster 56 times than soft performance, and the correlation coefficients at least 80% with the absolute value are compared with off-line processing results. Finally, live demonstration is shown in the DE2 FPGA board, and the design is consisted of 16,605 logic elements.
Front-end amplifier of low-noise and tunable BW/Gain for portable biomedical signal acquisition
(2008)
Huang, Chun-Chieh
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Hung, Shao-Hang
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Chung, Jen-Feng
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Van, Lan-Da
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Lin, Chin-Teng
We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated Circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 mu m CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 mu W under +/- 1.5V supply.
Function-in-layout: A demonstration with bio-inspired hyperacuity chip
(2007-03-01)
Mozsary, Andras
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Chung, Jen-Feng
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Roska, Tamas
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電控工程研究所
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Institute of Electrical and Control Engineering
Below 100nm a new scenario is emerging in VLSI design: floorplanning and function are inherently interrelated. Using mainly local connectivity, wire delay and crosstalk problems are eliminated. A new design methodology is proposed, called function-in-layout, that possesses: regular layout, mainly local connectivity, functional 'parasitics'. A bio-inspired demonstration is presented, a hyperacuity chip, with 30 ps time difference detection using 0.35 mm complementary metal-oxide semiconductor (CMOS) technology. Copyright (C) 2006 John Wiley & Sons, Ltd.
Real-Time Embedded EEG-Based Brain-Computer Interface
(2009)
Ko, Li-Wei
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Tsai, I-Ling
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Yang, Fu-Shu
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Chung, Jen-Feng
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Lu, Shao-Wei
Online artifact rejection, feature extraction, and pattern recognition are essential to advance the Brain Computer Interface (BCI) technology so as to be practical for real-world applications. The goals of BCI system should be a small size, rugged, lightweight, and have low power consumption to meet the requirements of wearability, portability, and durability. This study proposes and implements a moving-windowed Independent Component Analysis (ICA) on a battery-powered, miniature, embedded BCI. This study also tests the embedded BCI on simulated and real EEG signals. Experimental results indicated that the efficacy of the online ICA decornposition is comparable with that of the offline version of the same algorithm, suggesting the feasibility of ICA for online analysis of EEG in a BCI. To demonstrate the feasibility of the wearable embedded BCI, this study also implements an online spectral analysis to the resultant component activations to continuously estimate subject's task performance in near real time.