Browsing by Author "Chung, S. S."

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Dimensional Dependences of the Dynamic-NBTI with 1.2 nm N20-ISSG oxynitrides
(2007)
Lai, Chao Sung
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Huang, D. C.
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Chung, S. S.
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電機學院
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College of Electrical and Computer Engineering
New Observations on the Regular and Irregular Noise Behavior in a Resistance Random Access Memory
(2014-01-01)
Chen, Scott C. H.
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Huang, Y. J.
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Chung, S. S.
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Lee, H. Y.
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Chen, Y. S.
In this paper, a new type of noise, different from the conventional Random Telegraph Noise (RTN), has been found and analyzed in a resistance random access memory (RRAM). The regular RTN signal is governed by the trapping and detrapping of the electrons. It will appear regularly with a two-level current and the amplitude of the RTN is smaller. However, an abnormal noise, called giant noise, was observed from the oxygen migration. The amplitude of the giant noise is much larger than the RTN one. Also, two different types of giant noise were observed depending on the movement of the oxygen vacancies. All of the above various types of noise might play an important role in the readout error in an RRAM. Therefore, these noise effects need further attention in the design of RRAM.
Reliability of ALD Hf-based high K gate stacks with optimized interfacial layer and pocket implant engineering
(2007)
Mao, A. Y.
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Lin, W. M.
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Yang, Cw.
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Hsieh, Y. S.
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Cheng, L. W.
Reliability of ALD (Atomic Layer Deposition) HfSiON high K gate stacks is greatly enhanced with a property engineered IL (Interfacial Layer) between the gate dielectrics and the Si substrate. We report that the HfSiON, while deposited on an optimized plasma-based IL containing [N], exhibits strong resistance to the bombardment from heavy pocket implant species, achieving significantly reduced leakage and excellent reliability characteristics, compared to the HfSiON without an optimized IL and to the silicon oxynitride control wafers.
Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
(2012-10-01)
Yang, C. L.
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Tsai, C. H.
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Li, C. I.
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Tzeng, C. Y.
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Lin, G. P.
In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.
The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
(2008)
Hsieh, E. R.
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Chang, Derrick W.
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Chung, S. S.
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Lin, Y. H.
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Tsai, C. H.
In this paper, the device performance in terms of its transport charactertitics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from. experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental verifications on rMOSFETs with both technologies with tensile-stress enhancement have been made. For SSOI devices, it shows the expected drain current enhancements. For the reliability evaluations, SOI shows a smaller lattice such that it exhibits a much worse hot carrier (HC) reliability, while SSOI device shows a poorer interface quality verified from the FN-stress experiment. In general, although SSOI exhibits a worse interface quality while its reliability is much better than that of SOI's. Moreover, SSOI device shows a very high injection velocity as a result of the high strain of the device which makes it successful for drain current enhancement.
Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm
(2006)
Lee, G. D.
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Chung, S. S.
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Mao, A. Y.
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Lin, W. M.
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Yang, C. W.
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1nm (EOT). With the scaling of gate oxide thickness into 1mn regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT = 10.2 angstrom) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide.