Browsing by Author "Chung, SH"

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A case study on the multistage IC final testing scheduling problem with reentry
(2004-04-18)
Pearn, WL
;
Chung, SH
;
Chen, AY
;
Yang, MH
;
工業工程與管理學系
The integrated-circuit final testing scheduling problem (ICFTSP) with reentry is a variation of the complex flow-shop scheduling problem, which is also a generalization of the classical reentrant flow batch process problem, and the identical parallel machine problem. In this paper, we present a case study on the ICFTSP with reentry, which is taken from a final testing shop floor in an integrated circuit manufacturing factory. For the case investigated, the jobs are clustered by their product types, which must be processed on groups of parallel machines at various process stages following the manufacturing sequence, which must be completed before the due dates. The job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. The objective is to schedule jobs without violating all constraints, while the total machine workload is minimized. Since the ICFTSP has reentry characteristic, and involves job processing precedence, serial-processing stage, batch-processing stage, job clusters, job-cluster dependent processing time, due dates, machine capacity, and sequence dependent setup time, it is more difficult to solve than the classical flow-shop scheduling problem. We present three fast network algorithms to efficiently solve the ICFTSP with reentry and provide a performance comparison between the three algorithms on eight test problems. (C) 2003 Elsevier B.V. All rights reserved.
A case study on the wafer probing scheduling problem
(2002-01-01)
Pearn, WL
;
Chung, SH
;
Yang, MH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The wafer probing scheduling problem (WPSP) is a practical generalization of the classical parallel-machine scheduling problem, which has many real-world applications, particularly, in the integrated circuit (IC) manufacturing industry. In this paper, a case study on the WPSP is presented, which is taken from a wafer probing shop floor in an IC manufacturing factory. For the WPSP case investigated, the jobs are clustered by their product types, which are processed on groups of identical parallel machines and must be completed before the due dates. The job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. The objective in this case is to seek a probing job schedule with minimum total machine workload. Since the WPSP case investigated involves constraints on job clusters, job-cluster dependent processing time, due dates, machine capacity, and sequentially dependent setup time, it is more difficult to solve than the classical parallel-machine scheduling problem. The WPSP is formulated as an integer programming problem and the problem solved using the powerful CPLEX with effective implementation strategies. An efficient solution procedure to solve the WPSP near-optimally is proposed.
A linear programming model for the control wafers downgrading problem
(2005-02-01)
Chung, SH
;
Pearn, WL
;
Kang, HY
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper considers the control wafers downgrading problem (CWDP) in the wafer fabrication photolithography area. The objective of the research is to minimize the total cost of control wafers, while maintaining the same level of production throughput. For the problem under a pulling control production environment, a linear programming model is presented to set the supply rate of new control wafers and the recycle and downgrading rates so as to minimize the total cost of control wafers. A numerical example is given to illustrate the practicality of the model. The sensitivity of the linear programming model solution to changes in the underlying parameter values is also investigated. The results demonstrate that the proposed model is an effective tool for determining the control wafers downgrading policy. This paper presents a linear programming model that considers the cost of new control wafers, recycle and downgrading control wafers in wafer fabrication. The proposed model improved the performance of control wafers management, and served as the basis for setting the usage rates of control wafers.
A service level model for the control wafers safety inventory problem
(2005-09-01)
Chung, SH
;
Kang, HY
;
Pearn, WL
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper considers the control wafers safety inventory problem (CWSIP) in the wafer fabrication photolithography area. The objective is to minimize the total cost of control wafers, where the cost includes new wafers cost, re-entrant cost and holding cost while maintaining the same level of production throughput. For the problem under pulling control production environment, a nonlinear programming model is presented to set safety inventory levels so as to minimize total cost of control wafers. A numerical example is given to illustrate the practicality of the model. The results demonstrate that the proposed model is an effective tool for determining the service level of safety inventory of control wafers for each grade.
A tool portfolio elimination mechanism (TPEM) for a wafer fab
(2004)
Chung, SH
;
Hsieh, MH
;
Liu, JC
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Wafer manufacturers usually face critical problems when making decisions regarding to the tool portfolio elimination, mainly due to the dramatic and frequent influences from their internal and external environments. This paper is aimed to develop a mechanism, named Tool Portfolio Elimination Mechanism (TPEM), to evaluate the impacts on production performance and capital expenditure, and to determine which equipment is suitable for pruning. In TPEM, there are four stages to decide tool portfolio elimination according to the PDCA cycle. Meanwhile, the simulation results show; that the fab production performance and cost are much improved by the TPEM algorithm. Especially, it can be applied and implemented to industry very quickly and easily.
Algorithms for the wafer probing scheduling problem with sequence-dependent set-up time and due date restrictions
(2004-11-01)
Pearn, WL
;
Chung, SH
;
Yang, MH
;
Chen, YH
;
交大名義發表
In this paper, we consider the wafer probing scheduling problem (WPSP) to sequence families of jobs on identical parallel machines with due date restrictions. The machine set-up time is sequentially dependent on the product types of the jobs processed on the machine. The objective is to minimize the total machine workload without violating the machine capacity and job due date restrictions. The WPSP is a variation of the classical parallel-machine scheduling problem, that can be transformed into the vehicle-routing problem with time windows (VRPTW). One can therefore solve the WPSP efficiently using existing VRPTW algorithms. We apply four existing savings algorithms presented in the literature including sequential, parallel, generalized, and matching based savings, and develop three modifications called the modified sequential, the compound matching based, and the modified compound matching-based savings algorithms, to solve the WPSP. Based on the characteristics of the wafer probing process, a set of test problems is generated for testing purposes. Computational results show that the three proposed modified algorithms perform remarkably well.
Analytic network process (ANP) approach for product mix planning in semiconductor fabricator
(2005-04-18)
Chung, SH
;
Lee, AHI
;
Pearn, WL
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper proposes an application of the analytic network process (ANP) for the selection of product mix for efficient manufacturing in a semiconductor fabricator. In order to evaluate different product mixes, a hierarchical network model based on various factors and the interactions of factors is presented. By incorporating experts' opinion, a priority index can be calculated for each product mix studied, and a performance ranking of product mixes can be generated. The results provide guidance to a fab regarding strategies for accepting orders to maximize the manufacturing efficiency in considering the aspects of product, equipment efficiency and finance. The model can be easily understood and followed by administrators to determine the most efficient product mix for a fab. (c) 2004 Elsevier B.V. All rights reserved.
Control wafers inventory management in the wafer fabrication photolithography area
(2005-04-01)
Chung, SH
;
Pearn, WL
;
Kang, HY
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
An important variable affecting the production throughput in the wafer fabrication photolithography area is the work-in-process (WIP) level of control wafers. Previous research work has focused on control wafers downgrading problem, and little work has been done for WIP level of control wafers. The objective of this paper is to develop methods for estimating the WIP level of control wafers for each grade, while maintaining the same level of production throughput. Two factors are considered, the re-entrant of control wafers within the same grade and the downgrading of control wafers among different grades. Under pulling control production environment, a multi-loop algorithm is developed for estimating the WIP control wafers for each grade. We conduct some simulation experiments based on a real-world factory production environment to demonstrate the effectiveness of the proposed algorithm. The results show that the algorithm is an efficient tool for estimating the cycle time and WIP level for each grade of control wafers.
Cycle time estimation for wafer fab with engineering lots
(2002-02-01)
Chung, SH
;
Huang, HW
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Due to the interaction between the process complexity and equipment diversity in a wafer fab, it is rather difficult to estimate the material flow time of wafer lots. Facing competition, it is common for a wafer fab to produce a certain quantity of engineering lots. However, introducing engineering lots into the factory will increase the complexity of the material flow control and the difficulty in cycle time estimation. The purpose of this paper is to develop cycle time estimation algorithms for a wafer fab by analyzing the material flow characteristics. Simulation results have shown that the algorithm is capable of generating satisfactory cycle time estimations with or without existing engineering lots.
Job order releasing and throughput planning for multi-priority orders in wafer fabs
(2003-01-01)
Chung, SH
;
Pearn, WL
;
Lee, AHI
;
Ke, WT
;
工業工程與管理學系
To meet the production target of multi-level (multiple priority rank) orders in wafer fabs, this paper uses a hierarchical framework based on a mathematical model, and without the assistance of any simulation tool, to build a production scheduling system to plan wafer lot releasing sequence and time. This system first applies capacity loading analysis to set up the batch policy for each level (rank) of orders. Next, the production cycle time of each product level is estimated with considerations of batching and loading factor. The cycle time is then used to derive system control parameters such as the most appropriate level of work in process (WIP) and the number of daily operations on the bottleneck workstation. Lastly, a Constant WIP mechanism is applied to establish a wafer release sequence table and a throughput timetable. The due date designation for each specific order can hence be confirmed. With the comparison with the result of simulation, it shows that under the designed system the performance and planning measures in the master production schedule can be drawn up quickly and accurately, and the system throughput target and due date satisfaction can be achieved. Overall, the proposed production scheduling system is both effective and practicable, and the planning results are supportive for good target planning and production activity control.
Minimizing the total machine workload for the wafer probing scheduling problem
(2002-02-01)
Pearn, WL
;
Chung, SH
;
Yang, MH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The Wafer Probing Scheduling Problem (WPSP) is a practical generalization of the parallel-machine scheduling problem, which has many real-world applications, particularly, in the Integrated Circuit (IC) manufacturing industry. In the wafer probing factories, the jobs are clustered by their product types, which must be processed on groups of identical parallel machines and be completed before the due dates. The job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. Since the wafer probing scheduling problem involves constraints on job clusters, job-cluster dependent processing time, due dates, machine capacity, and sequentially dependent setup time, it is more difficult to solve than the classical parallel-machine scheduling problem. In this paper, we consider the WPSP and formulate the WPSP as an integer programming problem to minimize the total machine workload. We demonstrate the applicability of the integer programming model by solving a real-world example taken from a wafer probing shop floor in an IC manufacturing factory.
Product mix optimization for semiconductor manufacturing based on AHP and ANP analysis
(2005-06-01)
Chung, SH
;
Lee, AHI
;
Pearn, WL
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
In a competitive market, a company needs to utilize its available capacity efficiently in order to acquire high profit. The purpose of this paper is to present effective approaches to find a set of product mix optimal for the company to achieve the optimal manufacturing. Analytic hierarchy process ( AHP) and analytic network process ( ANP) approaches are taken to analyse multiple process inputs and outputs, incorporating experts' opinion on their priority of importance, to obtain optimal product mixes for semiconductor production. The results provide guidance to the fabricator regarding strategies for accepting orders to maximize the manufacturing efficiency and the profit, while simultaneously considering other important input and output factors for maintaining manufacturing smoothness.
The block-based cycle time estimation algorithm for wafer fabrication factories
(1999-12-01)
Chung, SH
;
Huang, HW
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
Cycle time is both an important performance measure and requisite input data for performing production planning. However, the interactive effects between some factors such as process complexity and variety of workstations, leads to difficulty in estimating cycle time. To solve these problems, this study developed a block-based cycle time estimation algorithm, called BBCT, to estimate the total cycle time for each kind of wafer process. Process was divided into numerous blocks. The block cycle time is induced by batch and loading issues. The BBCT algorithm is used to derive the cycle time induced by the batch issue according to the process characteristics within each block. A queuing time model is used to derive the waiting time resulting from the loading issue. The simulation results show that the cycle time estimation performance is much improved by the BBCT algorithm. Significance: The proposed BBCT algorithm can improve the performance of cycle time estimation, and served as the basis for setting production targets.
The integrated circuit packaging scheduling problem (ICPSP): A case study
(2005-09-01)
Pearn, WL
;
Chung, SH
;
Yang, MH
;
Chen, CY
;
工業工程與管理學系
The integrated-circuit-packaging scheduling problem (ICPSP) is a variation of the flexible flow-shop scheduling problem, which is also a generalization of the classical flow-shop and the identical parallel-machine problems. In this paper, we present a case study on the ICPSP. For the ICPSP we investigate, the jobs are clustered by their product types, which must be processed on groups of machines at various process stages following the manufacturing sequence, and be completed before the due dates. The job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. We present two efficient solution procedures to solve the ICPSP case. We generate a set of 11 ICPSP problems, which involve various setup time, processing time, and due date factors. The proposed savings approaches are shown to perform efficiently in solving the ICPSP. Significance: The integrated-circuit-packaging scheduling problem (ICPSP) is a practical but complex scheduling problem, which has many real world applications. The proposed approaches show the superiority to the traditional dispatch rules and solve the ICPSP efficiently.
The scheduling for parallel machines with periodic maintenance and setup activities
(2005)
Chung, SH
;
Tai, YT
;
Tsai, PH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper tackled a parallel scheduling problem for identical machines with periodic maintenance and sequence-independent setup times under a hybrid make-to-order (MTO) and make-to-stock (MTS) environment. Such a production environment is apparent in many capital-intensive and highly competitive high-tech industries; for example, the thin-film-transistor liquid-crystal-display (TFT LCD) industry. To fully exploit expensive machines, maximum throughput is the objective with the constraints of meeting the promised customer orders in each planning period. In this paper, the time interval of maintenance period is a constant. Hence, the planning period is set equal to corresponding maintenance period in order to reduce the problem complexity. Under such environment and Lime bucket setting, an integer programming (IP) model is developed to find the optimal production quantity and production sequence for each machine for throughput maximization. Finally, a practical example is given to demonstrate the applicability of the proposed IP model to cell assembly of a LCD factory.
The TOC-based algorithm for solving product mix problems
(1998-01-01)
Hsu, TC
;
Chung, SH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The five steps of the theory of constraints (TOC) emphasize exploiting constraints in order to increase the throughput of a system. The product mix decision is one application of the TOC five steps. However, these steps were considered to be implicit or incomplete, the criticism being that they result in deriving an infeasible solution when a plant has multiple resource constraints. This paper follows the essence of these five steps and presents an explicit algorithm to address the problem. When testing its effectiveness by using a dual-simplex method with bounded variables, this algorithm gives the same result in each iteration.
The TOC-based algorithm for solving product mix problems
(1998-01-01)
Hsu, TC
;
Chung, SH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The five steps of the theory of constraints (TOC) emphasize exploiting constraints in order to increase the throughput of a system. The product mix decision is one application of the TOC five steps. However, these steps were considered to be implicit or incomplete, the criticism being that they result in deriving an infeasible solution when a plant has multiple resource constraints. This paper follows the essence of these five steps and presents an explicit algorithm to address the problem. When testing its effectiveness by using a dual-simplex method with bounded variables, this algorithm gives the same result in each iteration.
The wafer probing scheduling problem (WPSP)
(2002-08-01)
Pearn, WL
;
Chung, SH
;
Yang, MH
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
The wafer probing scheduling problem (WPSP) is a variation of the parallel-machine scheduling problem, which has many real-world applications, particularly, in the integrated circuit (IC) manufacturing industry. In the wafer probing factories, the jobs are clustered by their product types, which must be processed on groups of identical parallel machines and be completed before the due dates. Further, the job processing time depends on the product type, and the machine setup time is sequence dependent on the orders of jobs processed. Since the wafer probing scheduling problem involves constraints on job clusters, job-cluster dependent processing time, due dates, machine capacity, and sequence dependent setup time, it is more difficult to solve than the classical parallel-machine scheduling problem. In this paper, we formulate the WPSP as an integer programming problem. We also transform the WPSP into the vehicle routing problem with time windows (VRPTW), a well-known network routing problem which has been investigated extensively. An illustrative example is given to demonstrate the proposed transformation. Based on the provided transformation, we present three efficient algorithms to solve the WPSP near-optimally.
Using constraint satisfaction approach to solve the capacity allocation problem for photolithography area
(2006)
Chung, SH
;
Huang, CY
;
Lee, AHI
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This paper addresses the capacity allocation problem for photolithography area (CAPPA) under an advanced technology environment. The CAPPA problem has two characteristics: process window and machine dedication. Process window means that a wafer needs to be processed on machines that can satisfy its process capability (process specification). Machine dedication means that after the first critical layer of a wafer lot is being processed on a certain machine, subsequent critical layers of this lot must be processed on the same machine to ensure good quality of final products. A production plan, constructed without considering the above two characteristics, is difficult to execute and to achieve its production targets. Thus, we model the CAPPA problem as a constraint satisfaction problem (CSP), which uses an efficient search algorithm to obtain a feasible solution. Additionally, we propose an upper bound of load unbalance estimation to reduce the search space of CSP for searching an optimal solution. Experimental results show that the proposed model is useful in solving the CAPPA problem in an efficient way.