Browsing by Author "Chung, Sheng-Ti"

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Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas Annealing
(2019-08-14)
Chung, Sheng-Ti
;
Huang, Yi-Chin
;
Fu, Yen-Chun
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper proposes a chemical pre-treatment process to reduce sulfate prior to atomic layer deposition of Al2O3 gate dielectrics on n-doped In0.7Ga0.3As layers to form metal oxide semiconductor capacitors (MOSCAPs). Cleaning with methanol was done after hydrogen chloride etching and ammonium sulfide passivation. X-ray photoelectron spectroscopy performed on the sample with methanol cleaning indicated that its native oxide regrowth was effectively prevented on the sulfur-passivated In0.7Ga0.3As surface under air exposure. By analysis using atomic force microscopy of the sample cleaned using methanol, no further increase of surface roughness was observed after 5 months of air exposure. In addition, a mid-gap interface defect density (D-it) of 1.3 x 10(12) cm(-2) eV(-1) was obtained from this sample. After forming gas annealing (FGA), the D-it was improved significantly, to a value below 10(12) cm(-2) eV(-1). The obtained data indicate that the combination of chemical pre-treatment and FGA is advantageous to passivating the trap states on In0.7Ga0.3As MOSCAPs. (C) 2019 The Electrochemical Society.
Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing
(2020-01-01)
Chung, Sheng-Ti
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 & x00B0;C, steeper S.S. and I_on& x002F;I_off> 10(7) could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 & x00B0;C possessed lower I_off and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.
High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications
(2017-05-01)
Sung, Po-Jung
;
Cho, Ta-Chun
;
Hou, Fu-Ju
;
Hsueh, Fu-Kuo
;
Chung, Sheng-Ti
In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S. S.) of 65 mV/decade with ION/IOFF > 10(9); strained JL bulk FinFETs show an S. S. of 75 mV/decade with I-ON/I-OFF > 10(7). For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ID-VG curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ID and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.