Browsing by Author "Chung, Szu-Chi"

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A 3.40ms/GF(p(521)) and 2.77ms/GF(2(521)) DF-ECC Processor with Side-Channel Attack Resistance
(2013-01-01)
Lee, Jen-Wei
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Chung, Szu-Chi
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Chang, Hsie-Chia
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Lee, Chen-Yi
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交大名義發表
A High-Performance Elliptic Curve Cryptographic Processor over GF(p) with SPA Resistance
(2012)
Chung, Szu-Chi
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Lee, Jen-Wei
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
In order to support high speed application such as cloud computing, we propose a new elliptic curve cryptographic (ECC) processor architecture. The proposed processor includes a 3 pipelined-stage full-word Montgomery multiplier which requires much fewer execution cycles than that of previous methods. To reach real-time requirement, the time-cost pre-computation steps of Montgomery modular multiplication are achieved by hardware as well. Moreover, our proposed processor is resistant to the simple power analysis (SPA) attack by using the Montgomery ladder-based elliptic curve scalar multiplication (ECSM). Even the Montgomery ladder method inherently has operation overhead compared with traditional binary ECSM, both of hardware sharing and parallelization techniques are exploited to improve the hardware performance. Synthesized in TSMC 90nm CMOS technology, our proposed ECC processor performs a 256-bit ECSM in 120 mu s over prime field with 540K gate counts. This result is at least 25% better than relative works in terms of area-time (AT) product.
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor
(2012-01-01)
Lee, Jen-Wei
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Chung, Szu-Chi
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
Correlation power-analysis (CPA) attacks are a serious threat for cryptographic device because the key can be disclosed from data-dependent power consumption. Hiding power consumption of encryption circuit can increase the security against CPA attacks, but it results in a large overhead for cost, speed, and energy dissipation. Masking processed data such as randomized scalar or primary base point on elliptic curve is another approach to prevent CPA attacks. However, these methods requiring pre-computed data are not suitable for hardware implementation of real-time applications. In this paper, a new CPA countermeasure performing all field operations in a randomized Montgomery domain is proposed to eliminate the correlation between target and reference power traces. After implemented in 90-nm CMOS process, our protected 521-bit dual-field elliptic curve cryptographic (DF-ECC) processor can perform one elliptic curve scalar multiplication (ECSM) in 4.57ms over GF(p(521)) and 2.77ms over GF(2(409)) with 3.6% area and 3.8% power overhead. Experiments from an FPGA evaluation board demonstrate that the private key of unprotected device will be revealed within 10(3) power traces, whereas the same attacks on our proposal cannot successfully extract the key value even after 10(6) measurements.
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications
(2017-09-01)
Chung, Szu-Chi
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Yu, Chun-Yuan
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Lee, Sung-Shine
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Chang, Hsie-Chia
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Lee, Chen-Yi
In order to secure the communication in Internet of Things era, a low overhead power analysis countermeasure called uniform distribution random power generator is proposed for stream ciphers. To alter the power signature of protected circuit, ring oscillators, which act as unit power generators, are grouped in a systematic approach to generate additional power with uniform probability distribution. Experiments from the proposed evaluation framework demonstrate that the secret key of unprotected device can be disclosed within 103 power traces with standard differential power analysis attack, whereas the same attack mounted on the proposed scheme cannot be disclosed even after 106 measurements. Moreover, the area and the power overhead are reduced by at least 29% and 22% compared with the state-of-the-art works, respectively.
Efficient Hardware Architecture of eta(T) Pairing Accelerator Over Characteristic Three
(2015-01-01)
Chung, Szu-Chi
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Wu, Jing-Yu
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Fu, Hsing-Ping
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Lee, Jen-Wei
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Chang, Hsie-Chia
To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of eta(T) pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller\'s loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller\'s loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 x 0.97 mm(2). It performs a bilinear pairing computation over F(3(97)) in 4.76 mu s under 1.0 V supply and achieves 178% improvement to relative works in terms of area-time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3709) in 36.2 mu s is implemented and this result is at least 31% better than relative works in terms of AT product.
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
(2014-01-01)
Lee, Jen-Wei
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Chung, Szu-Chi
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
Elliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4-mm(2) 160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 mu J for one GF(p)/GF(2(m)) ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks.