Browsing by Author "Chung, YH"

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A method to characterize n(+)-polysilicon/oxide interface traps in ultrathin oxides
(2001-06-01)
Chang, KM
;
Chung, YH
;
Lee, TC
;
Sun, YL
;
電子工程學系及電子研究所
In this study, a new method to characterize the n(+)-polysilicon/oxide interface trap state by measuring the gate voltage-gate leakage current (Vg-Jg) characteristics under the low electric field is developed. These traps are neutral and consist of the fast and slow trap states located near the Fermi level of the n(+)-polyoxide. We use the first order rate equation to characterize the relationship between the gate leakage current and the gate voltage sweep rate. A simple formula to characterize the detrapping behavior of the slow trap states with the detrapping time constant was derived. It is important to find that the smaller detrapping time constant observed in a thinner oxide (2.5 nm) is due to the field enhanced detrapping effect. (C) 2001 The Electrochemical Society.
A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
(2001-10-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
Lin, JH
;
Deng, CG
In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 x 10(6) and also shows the off-state leakage current 100 times lower than those of the conventional ones at V-GS = -15 V and V-DS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.
Anomalous variations of OFF-state leakage current in poly-Si TFT under static stress
(2002-05-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we study the anomalous variations of the OFF-state leakage current (I-OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I-OFF can be attributed to 1) I-OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and 2) I-OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (similar to(V_stress - V_ - Dstress) /T-ox) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (similar toV_Dstress/L-CH).
Carrier capture and relaxation of self-assembled ZnTe/ZnSe quantum dots prepared under Volmer-Weber and Stranski-Krastanow growth modes
(2005-02-01)
Lee, ME
;
Yeh, YC
;
Chung, YH
;
Wu, CL
;
Yang, CS
The carrier capture and relaxation of type II ZnTe/ZnSe quantum dots have been investigated with ultrafast time-resolved photo luminescence upconversion. The carrier capture times were 7 and 38 ps for the Volmer-Weber mode and Stranski-Krastanow mode, respectively. We found that the carrier relaxation of QDs exhibits faster decay under the Volmer-Weber growth mode than under the Stranski-Krastanow growth mode. We attribute the difference of carrier relaxation to the wetting layer formed in the Stranski-Krastanow growth mode. (C) 2004 Elsevier B.V. All rights reserved.
Characterization of the novel polysilicon TFT with a subgate coupling structure
(2002-04-01)
Chang, KM
;
Chung, YH
;
Deng, CG
;
Chung, YF
;
Lin, JH
We have proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs.
Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress
(2001-10-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
Deng, CG
;
Lin, JH
We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G(m max)) in static stress, G(m max) in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: 1) breaking of weak bonds and 2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation.
Hot carrier induced degradation in the low temperature processed polycrystalline silicon thin film transistors using the dynamic stress
(2002-04-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The dynamic stress on low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) is studied under two different stress conditions. As compared to static stress. the enhanced degradation in poly-Si TFT can be observed in dynamic stress. The enhanced degradation in dynamic stress (V-g = 0-20 V, V-ds = 22 V) is due to (1) the impact ionization effect in the ON state (V-gs = 20 V, V-ds = 22 V), (2) the drain avalanche hot carrier effect in the OFF state (V-gs = 0 V, V-ds = 22 V), and (3) the transient current stressing effect (at the switching period), However, in the stress condition of V-gs = -20 V to 20 V, V-ds = 0 V. both the source and drain regions are equally damaged. As the falling time becomes shorter, the transient current will increase to cause more device degradation near drain. It is also found that the degradation is more serious in short channel device than that in long channel device. As the stress frequency increases, the degradation will be enhanced. Moreover, the reduced degradation under high stress temperature is clue to reduced hot carrier effect under high temperature stressing.
Thickness and stress polarity effects on the reliability of the low thermal budget polyoixdes
(2001-10-01)
Chang, KM
;
Chung, YH
;
Chen, HY
;
Lee, TC
;
Sun, YL
In this paper, the thickness and the stress polarity effects on the reliability of the low thermal budget polyoxides are investigated. The polyoxides are prepared by two methods: the low-temperature tetraethylorthosilicate (TEOS) polyoxide deposition and in the rapid thermal chamber in N2O ambient (RTN2O). It is observed that the thinner TEOS polyoxides exhibit higher charge to breakdown (Q(bd)) and larger stress polarity effect than those of the thicker TEOS polyoxides. However, for the RTN2O grown polyoxides from 8.5 nm to 12.9 run, they have the similar values of the Qbd and the stress polarity effects, The nitrogen atoms incorporated in the RTN2O grown polyoxides may be the reason to this less thickness dependence of the Q(bd). Higher barrier height is also observed for the RTN2O grown polyoxides than that of the deposited TEOS polyoxide to obtain a lower tunneling current under a fixed electric field.