Browsing by Author "Chung, Yung-Hui"

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A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS
(2015-03-01)
Chung, Yung-Hui
;
Wu, Jieh-Tsorng
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
(2009)
Chung, Yung-Hui
;
Wu, Jieh-Tsorng
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交大名義發表
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National Chiao Tung University
a 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power dissipation, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The linearity of the residue amplifier is enhanced by digital background calibration. The resolution of the comparators is improved by analog offset calibration. The ADC consumes 6mW from a 1V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34b. The FOM is 100 fJ per conversion-step.
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
(2010-11-01)
Chung, Yung-Hui
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ . V per conversion-step.