Browsing by Author "Cong, Jason"

Now showing 1 - 7 of 7

A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2018-01-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Tang, Adrian
;
Chen, Huan-Neng
A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2018-01-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Tang, Adrian
;
Chen, Huan-Neng
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2019-06-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Cho, Wei-Han
;
Huang, Rulin
This paper presents a millimeter-wave (127 GHz) CMOS transceiver with a digital pre-distortion capable PAM-4 modulator for contactless communications. The transmitter upconverts PAM-4 modulated baseband signals through a free-running 127-GHz oscillator and single-balanced mixer, and it delivers PAM-4 modulated carrier signals to a folded-dipole antenna, which is designed on a FR408HR substrate. The receiver's low-noise amplifier provides a 10-dB gain, and the self-mixer downconverts carrier-modulated PAM-4 signals to base-band signals without the necessity of carrier synchronization. The PAM-4 modulator pre-distorts the baseband signals and corrects the non-linear characteristics of the transmitter's upconversion mixer and the receiver's downconversion self-mixer. Designed and fabricated in a 65-nm CMOS process, the demonstrated system transfers 20 Gb/s of PAM-4 modulated data through a 1-mm air gap and consumes 79.5 mW (transmitter: 50.8 mW and receiver: 28.7 mW) of power under a 1.2-V supply, achieving a 3.98-pJ/bit energy efficiency. The communication distance is extended to 3 cm by inserting a dielectric waveguide between the same transceiver.
Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI)
(2017-12-01)
Kim, Yanghyo
;
Cho, Wei-Han
;
Du, Yuan
;
Cong, Jason
;
Itoh, Tatsuo
SMEM plus plus : A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing
(2018-01-01)
Cong, Jason
;
Guo, Licheng
;
Huang, Po-Tsang
;
Wei, Peng
;
Yu, Tianhe
SMEM plus plus : A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing
(2018-01-01)
Cong, Jason
;
Guo, Licheng
;
Huang, Po-Tsang
;
Wei, Peng
;
Yu, Tianhe
Next-generation sequencing motivates the research of FPGA acceleration for genome sequencing algorithms. The recently developed quadratic-time SMEM seeding algorithm becomes a time-consuming computation kernel in genome sequencing, but it has not been well studied. The fundamental challenge of accelerating the SMEM algorithm is to handle its large volume of random memory accesses. While the state-of-the-art SMEM accelerator attempts sacrifices the performance of individual processing elements to maximize the task-level parallelism, this methodology suffers a serious resource under utilization issue. Therefore, we propose SMEM++, a pipelined and time-multiplexed FPGA accelerator for SMEM algorithm. SMEM++ adopts the canonical non-blocking pipeline methodology and implements a fully pipelined accelerator with initiation interval equal to one. Moreover, we design a communication interface adapter to make the accelerator compatible to the target platform interface and increase its portability. Experiments on the Intel HARPv2 platform show that SMEM++ outperforms the original software by 24x, and outperforms the state-of-the-art SMEM accelerator design by 6.3x, with 43% less logic resource usage.
The SMEM Seeding Acceleration for DNA Sequence Alignment
(2016)
Chang, Mau-Chung Frank
;
Chen, Yu-Ting
;
Cong, Jason
;
Huang, Po-Tsang
;
Kuo, Chun-Liang
The advance of next-generation sequencing technology has dramatically reduced the cost of genome sequencing. However, processing and analyzing huge amounts of data collected from sequencers introduces significant computation challenges; these have become the bottleneck in many research and clinical applications. For such applications, read alignment is usually one of the most compute-intensive steps. Billions of reads generated from the sequencer need to be aligned to the long reference genome. Recent state-of-the-art software read aligners follow the seed-andextend model. In this paper we focus on accelerating the first seeding stage, which generates the seeds using the supermaximal exact match (SMEM) seeding algorithm. The two main challenges for accelerating this process are 1) how to process a huge number of short reads with high throughput, and 2) how to hide the frequent and long random memory access when we try to fetch the value of the reference genome. In this paper, we propose a scalable array-based architecture, which is composed by many processing engines (PEs) to process large amounts of data simultaneously for the demand of high throughput. Furthermore, we provide a tight software/hardware integration that realizes the proposed architecture on the Intel-Altera HARP system. With a 16-PE accelerator engine, we accelerate the SMEM algorithm by 4x, and the overall SMEM seeding stage by 26% when compared with 16-thread CPU execution. We further analyze the performance bottleneck of the design due to extensive DRAM accesses and discuss the possible improvements that are worthwhile to be explored in the future.