Browsing by Author "Current, Michael I."

Now showing 1 - 9 of 9

Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing
(2011-07-01)
Hsueh, Fu-Kuo
;
Lee, Yao-Jen
;
Lin, Kun-Lin
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Current, Michael I.
;
Wu, Ching-Yi
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 x 10(15) ion/cm(2), were annealed by microwave methods at temperatures below 500 degrees.C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross-sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications
(2017-05-01)
Sung, Po-Jung
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Cho, Ta-Chun
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Hou, Fu-Ju
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Hsueh, Fu-Kuo
;
Chung, Sheng-Ti
In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S. S.) of 65 mV/decade with ION/IOFF > 10(9); strained JL bulk FinFETs show an S. S. of 75 mV/decade with I-ON/I-OFF > 10(7). For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ID-VG curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ID and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.
Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks
(2013-10-01)
Lee, Yao-Jen
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Tsai, Bo-An
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Lai, Chiung-Hui
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Chen, Zheng-Yao
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Hsueh, Fu-Kuo
In this letter, low-temperature (480 degrees C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.
Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review
(2014-03-01)
Lee, Yao-Jen
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Cho, Ta-Chun
;
Chuang, Shang-Shiun
;
Hsueh, Fu-Kuo
;
Lu, Yu-Lun
Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C. Next, enhancing the substitutional carbon concentration ([C] sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.
Microwave Annealing
(2012)
Lee, Yao-Jen
;
Cho, T. -C.
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Chuang, S. -S.
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Hsueh, F. -K.
;
Lu, Y. -L.
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However the details of the kinetics and mechanisms for microwave annealing are far from well understood. Comparisons between MWA and RTA of dopants in implanted Si has been investigated to produce highly activated junctions. First, As, P-31, and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C.
Microwave Annealing of Phosphorus and Cluster Carbon Implanted (100) and (110) Si
(2013)
Cho, Ta-Chun
;
Lu, Yu-Lun
;
Yao, Jie-Yi
;
Lee, Yao-Jen
;
Sekar, Karuppanan
Effects of low-temperature (approximate to 500 degrees C) microwave annealing (MWA) of Cluster-Carbon (C-7) and Phosphorus implants are compared with rapid thermal annealing (RTA) at 900 and 1000 degrees C for (100) and (110)-Si substrates. MWA annealing resulted in high levels of substitutional Carbon, 1.57% for (100) Si and 0.99% for (110) Si for C-7 implants. Addition of high-dose Phosphorus implants resulted in lower but still useful substitutional Carbon levels, 1.44% for (100) Si and 0.68% for (110) Si after MWA. RTA annealing at higher temperatures resulted in greatly reduced substitutional Carbon levels and deeper Phosphorus junctions. The effects of subsequent anneals by MWA and RTA methods are reported. MWA is shown to be a promising method for high-channel tensile strain in nMOSFETs with a substantially lower thermal budget than RTA. (C) 2013 The Electrochemical Society. All rights reserved.
Susceptor Coupling for the Uniformity and Dopant Activation Efficiency in Implanted Si Under Fixed-Frequency Microwave Anneal
(2012-02-01)
Lee, Yao-Jen
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Hsueh, Fu-Kuo
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Current, Michael I.
;
Wu, Ching-Yi
;
Chao, Tien-Sheng
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, during conventional fixed-frequency microwave heating, standing wave patterns can be established in the microwave processing chamber, resulting in nodes and antinodes over the processing area, resulting in thermal variations over the process wafer. In this letter, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency microwave anneal are studied. The composition, number, and spacing of susceptor wafers were varied in a systematic fashion in these experiments.
Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices
(2017-01-01)
Chuang, Shang-Shiun
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Cho, Ta-Chun
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Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Chen, Henry J. H.
We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800 degrees C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of approximate to 15 nm, and peak concentration of approximate to 6 x 10(20) atoms/cm(3). The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA. (C) 2017 The Electrochemical Society. All rights reserved.