Browsing by Author "Deng, CG"

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A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
(2001-10-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
Lin, JH
;
Deng, CG
In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 x 10(6) and also shows the off-state leakage current 100 times lower than those of the conventional ones at V-GS = -15 V and V-DS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.
Characterization of the novel polysilicon TFT with a subgate coupling structure
(2002-04-01)
Chang, KM
;
Chung, YH
;
Deng, CG
;
Chung, YF
;
Lin, JH
We have proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs.
Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress
(2001-10-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
Deng, CG
;
Lin, JH
We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G(m max)) in static stress, G(m max) in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: 1) breaking of weak bonds and 2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation.