Browsing by Author "Diaz, Carlos H."

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A millisecond-anneal-assisted selective fully silicided (FUSI) gate process
(2008-09-01)
Lin, Da-Wen
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Wang, Maureen
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Cheng, Ming-Lung
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Sheu, Yi-Ming
;
Tarng, Bennet
We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (NISA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for PMOSFETs with the feature size down to 30 run. A 20% improvement in FUSI-gated PMOSFET I-on-I-off is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.
Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
(2020-08-01)
Chiang, Hung-Li
;
Chen, Tzu-Chiang
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Song, Ming-Yuan
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Chen, Yu-Sheng
;
Chiu, Jung-Piao
To increase the density of magnetoresistive random accessmemory (MRAM) beyond the 1T1MTJMRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (V-TH-V-HOLD) when the selector is turned on. Also, exponential-type selectorswould degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Omega . mu m(2) and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density similar to 1 MA/cm(2)) and threshold-type selectors (V-TH-V-HOLD similar to 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.
Electrical Characteristics of Al2O3/InSb MOSCAPs and the Effect of Postdeposition Annealing Temperatures
(2013-05-01)
Hai Dang Trinh
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Lin, Yueh Chin
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Chang, Edward Yi
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Lee, Ching-Ting
;
Wang, Shin-Yuan
The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C-V) characteristics exhibit low-frequency and asymmetrical C-V behaviors, in which capacitance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature > 300 degrees C. This degradation is closely related to the diffusion of In, Sb into Al2O3 as indicated by transmission electron microscopy analyses.
Electrical Characterization and Materials Stability Analysis of La2O3/HfO2 Composite Oxides on n-In0.53Ga0.47As MOS Capacitors With Different Annealing Temperatures
(2013-10-01)
Lin, Yueh Chin
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Trinh, Hai Dang
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Chuang, Ting Wei
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Iwai, Hiroshi
;
Kakushima, Kuniyuki
In this letter, a high-k composite oxide composed of La2O3 and HfO2 is investigated for n-In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La2O3 (0.8 nm)/HfO2(0.8 nm) on InGaAs with post deposition annealing at 500 degrees C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D-it) of 7.0 x 10(11) cm(-2)eV(-1), small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.
Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate
(2014-04-01)
Lin, Yueh-Chin
;
Huang, Mao-Lin
;
Chen, Chen-Yu
;
Chen, Meng-Ku
;
Lin, Hung-Ta
A low interface trap density (D-it) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance-voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interlace trap density D-it close to 5.5 x 10(11)cm(-2) eV(-1). The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future. (C) 2014 The Japan Society of Applied Physics
Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependent diffusion model
(2006-08-01)
Sheu, Yi-Ming
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Yang, Sheng-Jier
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Wang, Chih-Chiang
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Chang, Chih-Sheng
;
Chen, Ming-Jer
N-channel metal-oxide-semiconductor field effect transistors (MOSFETs) with a lightly doped well exhibit subthreshold current versus voltage (I-V) characteristics that are sensitive to shallow trench isolation (STI) mechanical stress. Such striking dependencies offer the opportunity to validate a proposed two-dimensional (2D) process model that relates the impurity diffusion to the mechanical stress throughout the substrate. With the assistance of sophisticated process/device simulations, the model appears to satisfactorily reproduce subthreshold I-V characteristics for different active area lengths and different substrate biases. The stress-dependent point defect equilibrium concentration and diffusion model are also implemented to evaluate the stress effect on transient enhanced diffusion.
Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs
(2009)
Chen, William Po-Nien
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Su, Pin
;
Goto, Ken-Ichi
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Diaz, Carlos H.
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電子工程學系及電子研究所
This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) R(sd) extraction method is also proven by simulated current-voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.