Browsing by Author "Du, Li"

Now showing 1 - 6 of 6

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection
(2017-04-01)
Du, Yuan
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Cho, Wei-Han
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Huang, Po-Tsang
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Li, Yilei
;
Wong, Chien-Heng
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm(2) in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 mu W/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications
(2018-01-01)
Li, Yilei
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Dhwaj, Kirti
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Wong, Chien-Heng
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Du, Yuan
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Du, Li
In this paper, a fully synthesizable all-digital transmitter (ADTX) is first proposed. This transmitter (TX) uses Cartesian architecture and supports wide-band quadratic-amplitude modulation with wide carrier frequency range. Furthermore, the design methodology for ADTX and corresponding bandpass filter is discussed. This TX is synthesized with digital register transfer level-graphic database system flow, and can be easily implemented in any standard CMOS technology. An exemplary TX is synthesized by TSMC 28-nm standard cell library with extremely small area (0.0009 mm(2)) and supports carrier frequency as high as 6 GHz with excellent error vector magnitude (<-30 dB). To the best of the authors' knowledge, this is the first work on a fully synthesizable design of RF transistors, allowing easy technology migration and portability.
A Reconfigurable 64-Dimension K-Means Clustering Accelerator With Adaptive Overflow Control
(2020-04-01)
Du, Li
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Du, Yuan
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Chang, Mau-Chung Frank
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交大名義發表
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National Chiao Tung University
This brief presents a novel reconfigurable $K$ -means clustering accelerator that is suitable for integration in both IoT and data center system. The high vector dimension reconfigurability and design cost reduction is achieved through vector-streaming and adaptive overflow control to adapt distance computation using as-needed precision (dynamic 16-bit fixed-point data format). A two-stage shift-bit counted comparator is proposed. It can determine most results through only turning on the shift-bit comparator (3-bit), reducing the power consumption by $7\times $ compared to the direct full dynamic range comparison. Four vectors with two cluster centroids are processed simultaneously. Up to 8-dimension cluster vectors are stored in local buffer to reduce data exchange between the main memory and the processing engine. A prototype accelerator was implemented in TSMC 65 nm. The accelerator occupied 0.26 mm(2) and can support up to 64-D vector clustering. It achieved 31.2M query vectors/s with 41-mW power consumption at 250-MHz clock (cluster number: 2, vector dimension: 64) and an energy efficiency of 0.41 TOPS/W at 30 MHz clock.
A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
(2018-01-01)
Du, Li
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Du, Yuan
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Li, Yilei
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Su, Junjie
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Kuan, Yen-Cheng
Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max-pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65-nm technology with a core size of 5 mm(2). The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350 mW, making it a promising hardware accelerator for intelligent IoT devices.
A Single Layer 3-D Touch Sensing System for Mobile Devices Application
(2018-02-01)
Du, Li
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Liu, Chun-Chen
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Zhang, Yan
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Li, Yilei
;
Du, Yuan
Touch sensing has been widely implemented as a main methodology to bridge human and machine interactions. The traditional touch sensing range is 2-D and therefore limits the user experience. To overcome these limitations, we propose a novel 3-D contactless touch sensing called Airtouch system, which improves user experience by remotely detecting single/multi-finger position. A single layer touch panel with triangle-shaped electrodes is proposed to achieve multitouch detection capability as well as manufacturing cost reduction. Moreover, an oscillator-based-capacitive touch sensing circuit is implemented as the sensing hardware with the bootstrapping technique to eliminate the interchannel coupling effects. To further improve the system accuracy, a grouping algorithm is proposed to group the useful channels' data and filter out hardware noise impact. Finally, improved algorithms are proposed to eliminate the fringing capacitance effect and achieve accurate finger position estimation. EM simulation proved that the proposed algorithm reduced the maximum systematic error by 11 dB in the horizontal position detection. The proposed system consumes 2.3 mW and is fully compatible with existing mobile device environments. A prototype is built to demonstrate that the system can successfully detect finger movement in a vertical direction up to 6 cm and achieve a horizontal resolution up to 0.6 cm at 1 cm finger-height. As a new interface for human and machine interactions, this system offers great potential in finger movement detection and gesture recognition for small-sized electronics and advanced human interactive games for mobile device.
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
(2019-10-01)
Du, Yuan
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Du, Li
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Gu, Xuefeng
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Du, Jieqiong
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Wang, X. Shawn
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric, the engine's mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm(2). The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem-classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.