Browsing by Author "Dung, LR"

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A content-based methodology for power-aware motion estimation architecture
(2005-10-01)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel power-aware motion estimation algorithm, called adaptive content-based subsample algorithm (ACSA), for battery-powered multimedia devices. While the battery status changes, the architecture adaptively performs graceful tradeoffs between power consumption and compression quality. As the available energy decreases, the algorithm raises the subsample rate for maximizing battery lifetime. Differing from the existing subsample algorithms, the content-based algorithm first extracts edge pixels from a macro-block and then subsamples the remaining low-frequency part. In this way, we can alleviate the aliasing problem and thus keep the quality degradation low as the subsample rate increases. As shown in experimental results, the architecture can dynamically operate at different power consumption modes with little quality degradation according to the remaining capacity of battery pack while the power overhead of edge extraction is under 0.8%.
A content-based motion estimation algorithm for power-aware architecture
(2003)
Cheng, HW
;
Dung, LR
;
Yen, JH
;
Wang, JJ
;
電控工程研究所
This paper presents a novel power-aware architecture, called the vario-power architecture, for motion estimation. Based on the proposed content-based subsample algorithm, the architecture can operate at different power consumption modes with little quality degradation and the switching of power mode can be done dynamically. As shown in the simulation results, the power consumption can be significantly reduced by simply change the threshold parameters while the quality degradations are little.
A maskable memory architecture for rank-order filtering
(2004-05-01)
Dung, LR
;
Lin, MC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel implementation Of rank-order filtering using maskable memory. Based on a generic bit-sliced rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank order filtering, threshold decomposition and polarization. In conventional designs, these operations are usually implemented as logic circuit and require complex computation. Using the memory-oriented architecture, the proposed rank-order filter can benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read partial write, and pipelined processing. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits,for parallel read/write operations. Combining the bit-sliced read with polarization selector allows PMM to perform polar determination while the partial write achieves polarization. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in term -3 of cost and speed(I).
A maskable memory architecture for rank-order filtering
(2004-01-01)
Lin, MC
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel implementation of rank-order filtering using maskable memory. Based on a bit-serial rank-order filtering algorithm the proposed design uses a special-defined memory, called parallel maskable memory (PMM) to realize major operations of rank-order filtering, polarization and update. Using the memory-orient architecture, the proposed rank-order filter can. benefit from high flexibility, low cost and high speed. PMM has features of bit-sliced read, partial write, and pipelined datapath. Bit-sliced read and partial write are driven by maskable registers. The maskable registers allows PMM to configure operating bits. The bit-sliced read with a polarization selector allows PMM to perform polar determination while the partial write helps next-bit update. Recursively combining the bit-sliced read and partial write, PMM can effectively realizes rank-order filtering in terms of cost and speed.
A novel vario-power architecture of motion estimation using a content-based subsample algorithm
(2003)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Motion estimation is a key element in many video compression systems which tends to dominate computational and hence power requirements. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is highly required. To meet the requirement, this paper presents a novel power-aware architecture, called the vario-power architecture, for motion estimation. Based on a semi-systolic array with content-based subsample algorithm, the architecture dynamically disable some processing elements to reduce the power consumption. By performing the edge extraction first, a threshold was then set as the criterion of whether to enable/disable processing elements and thus the switch activities of system can be reduced. As the result, the architecture may dynamically operate at different power consumption modes according to the remaining capacity of battery pack with little quality degradation.
A reconfigurable architecture for DSP system-on-chip
(2001-07-01)
Dung, LR
;
Lee, YL
;
Wu, CM
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Digital signal processing (DSP) has been moving into the era of system-on-chip (SoC) design. Yet, the development of SoC architectures is rather intellectual-property (IP)-based and presents several challenges to designers, notably in the transformation of algorithms and the integration of IP cores. Tams, this paper employs Petri nets to model the DSP algorithms and presents a novel architecture for rapid design of digital signal processing. The architecture features a reconfigurable scheduler to dynamically schedule DSP operations onto processing elements and, thus, tolerates nondeterministic latencies of operations due to communication overhead and memory caching. Using the architecture, the designer can seamlessly plug in different IP cores to explore the alternative solutions and upgrade the architecture by reconfiguring the scheduler.
A vario-power ME architecture using content-based subsample algorithm
(2004-02-01)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
The Motion estimator is a key element in many video compression systems and it tends to dominate the power consumption in them. With increasing demand of portable, power-aware multimedia devices, an architecture that can be flexible in both power consumption and compression quality is essential. To meet this requirement, this paper presents a novel power-aware architecture, called the Vario-Power Architecture, for the motion estimation. Based on a semi-systolic array with the content-based subsample algorithm, the architecture real-time disables some processing elements to reduce power consumption. By performing the edge extraction first, a threshold is then set as the criterion of whether to enable or disable processing elements and thus the switch activities of the system can be reduced. As the simulation shows, the architecture may operate at different power consumption modes according to the remaining capacity of the battery pack, giving little quality degradation and the power overhead under 0.36%.(1)
An automated IP synthesizer for limited-resource DWT processor
(2002)
Wei, TH
;
Huang, SR
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a systematic design methodology for 1-D/2-D DWT processor based on a novel limited-resource scheduling algorithm. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Based on the limited-resource scheduling algorithm an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.
An IP synthesizer for limited-resource DWT processor
(2004-12-01)
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a VLSI design methodology for the MAC-level DWT/IDWT processor based on a novel limited-resource scheduling algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filtering has been developed for the scheduling of the MAC-level DWT/IDWT signal processing. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Because the memory for the inter-octave is considered with the register of FIR filter, the memory size is less than the traditional architecture. Besides, based on the limited-resource scheduling algorithm, an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPS can be efficiently realized by tuning the parameters and applied for signal processing applications.
Design of power-aware multiplier with graceful quality-power trade-offs
(2005)
Yen, JH
;
Dung, LR
;
Shen, CY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.
Dynamic range improvement of multistage multibit Sigma Delta modulator for low oversampling ratios
(2005-02-01)
Chang, TH
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents an improved architecture of the multistage multibit sigma-delta modulators (EAMs) for wide-band applications. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCEFF). Because of in-band zeros introduced by internal loop filters, the proposed architecture enhances the suppression of the in-band quantization noise at a low OSR. The HQCRFF-based modulator with single-bit quantizer has two modes of operation, modulation and oscillation. When the HQCRFF-based modulator is operating in oscillation mode, the feedback path from the quantizer output to the input summing node is disabled and hence the modulator output is free of the quantization noise terms. Although operating in oscillation mode is not allowed for single-stage SigmaDeltaM, the oscillation of HQCRFF-based modulator can improve dynamic range (DR) of the multistage (MASH) SigmaDeltaM. The key to improving DR is to use HQCRFF-based modulator in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. According to theoretical and numerical analysis, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.
EFBLA: a two-phase matching algorithm for fast motion estimation
(2004-05-27)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A novel motion estimation algorithm that contains edge matching and block matching is presented. The edge matching reduces candidates for the block matching that performs accurate searching. Thus, the two-phase procedure speeds up motion estimation. As a result, edge-matching first block-matching last algorithm (EFBLA) may significantly save the computation load by 93.9%.
EFBLA: A two-phase matching algorithm for fast motion estimation
(2002)
Cheng, HW
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a novel matching algorithm for fast motion estimation. The algorithm, called the Edge-matching First Block-matching Last Algorithm (EFBLA), first employs the edge-matching procedure to determine candidate motion vectors and then performs the conventional block matching with the SAD criteria on the candidates. The edge-matching procedure features low computation load and high degree of data reusability; therefore, it requires fewer operations and lower memory size compared with the full search algorithm. As the result of benchmarking and comparing to the full search algorithm, EFBLA may significantly save the computation load by 93.9% while the degradation of PSNR is very little.
Modeling and formal verification of dataflow graph in system-level design using Petri net
(2005)
Chiang, TH
;
Dung, LR
;
Yaung, MF
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Formal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.
On improving dynamic range of wideband multistage Sigma Delta modulator using nonlinear oscillation
(2005)
Chang, TH
;
Dung, LR
;
Guo, JY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents an improved architecture of the multistage (MASH) multibit sigma-delta modulators (Sigma Delta Ms). The architecture can be immune to circuit nonidealities over a large portion of input range when oversampling ratio (OSR) is low, and hence the dynamic range (DR) can be improved. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). The key to improving DR is to use HQCRFF-based single-bit structure in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. In addition, because of the in-band zeros introduced by the resonators, the proposed architecture enhances the suppression of the in-band quantization noise for wideband applications. As the results of simulation, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.
On multiple-voltage high-level synthesis using algorithmic transformations
(2004-12-01)
Dung, LR
;
Yang, HC
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a multiple-voltage high-level synthesis approach for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the iteration period (IP) as much as possible. The minimization of IP results in high task mobilities. Finally, we can assign tasks with high mobilities to low-voltage components and, thus, minimize energy under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. In the case of the third-order IIR filter, the proposed approach can save up to 40.2% of power consumption.
On reducing leakage quantization noise of multistage Sigma Delta modulator using nonlinear oscillation
(2005)
Chang, TH
;
Dung, LR
;
Guo, JY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents an improved architecture of the multistage (MASH) multibit sigma-delta modulators (Sigma Delta Ms). The architecture can be immune to circuit nonidealities over a large portion of input range when oversampling ratio (OSR) is low, and hence the dynamic range (DR) can be improved. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). The key to improving DR is to use HQCRFF-based single-bit structure in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. In addition, because of the in-band zeros introduced by the resonators, the proposed architecture enhances the suppression of the in-band quantization noise for wideband applications. As the results of simulation, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.
Resonator-based multi-stage Sigma Delta modulator for wideband applications with improved dynamic range
(2004-05-27)
Chang, TH
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A new design methodology for wideband, multi-stage, multi-bit YEA modulators (SigmaDeltaMs) with improved dynamic range, is presented. The key to improving dynamic range is to have the first stage oscillated, then the coarse quantisation noise vanishes and hence circuit nonlinearities do not cause a leakage quantisation noise problem. Based on the proposed methodology, a fourth-order four-bit SigmaDeltaM can achieve the dynamic range of 80 dB at the OSR of 8 without using additional calibration techniques.
VLSI implememtation for MAC-level DWT architecture
(2002)
Huang, SR
;
Dung, LR
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filter has been developed for the scheduling of the MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture.