Browsing by Author "Dung, Lan-Rong"

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A 2.5-V 14-bit, 180-mW cascaded Sigma Delta ADC for ADSL2+ application
(2007-11-01)
Chang, Teng-Hung
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Dung, Lan-Rong
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Guo, Jwin-Yen
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Yang, Kai-Jiun
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電控工程研究所
This paper presents a sigma-delta (Sigma Delta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 Sigma Delta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25 mu tm CMOS technology, in a 2.8 mm(2) active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
A Content-Motion-Aware Motion Estimation for Quality-Stationary Video Coding
(2010)
Lin, Meng-Chun
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Dung, Lan-Rong
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電控工程研究所
;
Institute of Electrical and Control Engineering
The block-matching motion estimation has been aggressively developed for years. Many papers have presented fast block-matching algorithms (FBMAs) for the reduction of computation complexity. Nevertheless, their results, in terms of video quality and bitrate, are rather content-varying. Very few FBMAs can result in stationary or quasistationary video quality for different motion types of video content. Instead of using multiple search algorithms, this paper proposes a quality-stationary motion estimation with a unified search mechanism. This paper presents a content-motion-aware motion estimation for quality-stationary video coding. Under the rate control mechanism, the proposed motion estimation, based on subsample approach, adaptively adjusts the subsample ratio with the motion-level of video sequence to keep the degradation of video quality low. The proposed approach is a companion for all kinds of FBMAs in H. 264/AVC. As shown in experimental results, the proposed approach can produce stationary quality. Comparing with the full-search block-matching algorithm, the quality degradation is less than 0.36 dB while the average saving of power consumption is 69.6%. When applying the proposed approach for the fast motion estimation (FME) algorithm in H. 264/AVC JM reference software, the proposed approach can save 62.2% of the power consumption while the quality degradation is less than 0.27 dB.
A Digital Boost Converter for Fuel Cell Current Regulation in Hybrid Power Systems
(2016)
Dung, Lan-Rong
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Yu, Hung-Ming
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Yuan, Hsiang-Fu
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電機工程學系
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電控工程研究所
Fuel cell (FC)/lithium-ion battery hybrid power system (HPS) gradually becomes a powerful energy source in the future. This paper presents a digital boost converter for FC current regulation in the HPS with a dual-battery energy storage unit (ESU). The digital boost converter regulates the FC current in order to control the FC power generation. Simulations have been conducted in PSIM environment, and the digital controller is implemented with a Microchip dsPIC33FJ06GS202 16-bit microcontroller. Experimental results show that the efficiency of power conversion can reach to 85%.
A Hybrid Fuel Cell-Battery Power System
(2014)
Yuan, Hsiang-Fu
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Dung, Lan-Rong
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資訊工程學系
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電機學院
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Department of Computer Science
This paper presents a new hybrid power system with battery depth-of-discharge (DOD) management for extending battery cycle life and system service time. The proposed power system consists of a power management system, a dual-battery unit, a fuel cell (FC) stack, and two dc/dc unidirectional power converters. The dual-battery unit serves as the primary power source, while the FC stack serves as the secondary power source. The proposed power management is based on a state-machine-based mechanism, using a battery interchanging strategy to limit batteries operating within a given DOD range. The state-machine-based mechanism is employed for reducing the effects of battery overcharging or overdischarging; thus, it can significantly improve the battery life time. In addition, this algorithm has the ability to distribute the power flow efficiently between the dual batteries and the FC stack, and also to keep providing a stable and continuous energy output for the load. A current-mode control dc/dc boost converter is designed to regulate the FC current and try to maximize the FC power for battery charging time reduction. The proposed hybrid system introduced in this paper is designed and implemented with a 20W proton exchange membrane fuel cell (PEMFC) stack and two 12Ah lithium iron phosphate (LiFePO4) batteries. The experimental results of capacity fades on various DOD tests verify the usefulness of the proposed fuel cell/dual batteries hybrid power system. The comparison of life improvement is also shown in test results.
A Hybrid Fuel Cell-Battery Power System
(2014-01-01)
Yuan, Hsiang-Fu
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Dung, Lan-Rong
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a new hybrid power system with battery depth-of-discharge (DOD) management for extending battery cycle life and system service time. The proposed power system consists of a power management system, a dual battery unit, a fuel cell (EC) stack, and two de/de unidirectional power converters. The dual-battery unit serves as the primary power source, while the FC stack serves as the secondary power source. The proposed power management is based on a state machine -based mechanism, using a battery interchanging strategy to limit batteries operating within a given DOD range. The state machine -based mechanism is employed for reducing the effects of battery overcharging or overdischarging; thus, it can significantly improve the battery life time. In addition, this algorithm has the ability to distribute the power flow efficiently between the dual batteries and the FC stack, and also to keep providing a stable and continuous energy output for the load. A current mode control dc/dc boost converter is designed to regulate the EC current and try to maximize the FC power for battery charging time reduction. The proposed hybrid system introduced in this paper is designed and implemented with a 20W proton exchange membrane fuel cell (PEMEC) stack and two I2Ah lithium iron phosphate (LiFePO4) batteries. The experimental results of capacity fades on various DOD tests verify the usefulness of the proposed fuel cell/dual batteries hybrid power system. The comparison of life improvement is also shown in test results.
A Lithium-Ion Battery Simulator Based on a Diffusion and Switching Overpotential Hybrid Model for Dynamic Discharging Behavior and Runtime Predictions
(2016-01-01)
Dung, Lan-Rong
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Yuan, Hsiang-Fu
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Yen, Jieh-Hwang
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She, Chien-Hua
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Lee, Ming-Han
A new battery simulator based on a hybrid model is proposed in this paper for dynamic discharging behavior and runtime predictions in existing electronic simulation environments, e.g., PSIM, so it can help power circuit designers to develop and optimize their battery-powered electronic systems. The hybrid battery model combines a diffusion model and a switching overpotential model, which automatically switches overpotential resistance mode or overpotential voltage mode to accurately describe the voltage difference between battery electro-motive force (EMF) and terminal voltage. Therefore, this simulator can simply run in an electronic simulation software with less computational efforts and estimate battery performances by further considering nonlinear capacity effects. A linear extrapolation technique is adopted for extracting model parameters from constant current discharging tests, so the EMF hysteresis problem is avoided. For model validation, experiments and simulations in MATLAB and PSIM environments are conducted with six different profiles, including constant loads, an interrupted load, increasing and decreasing loads and a varying load. The results confirm the usefulness and accuracy of the proposed simulator. The behavior and runtime prediction errors can be as low as 3.1% and 1.2%, respectively.
A Modified H.264 Intra-frame Video Encoder for Capsule Endoscope
(2008-01-01)
Dung, Lan-Rong
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Wu, Yin-Yi
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Lai, Hsin-Cheng
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Weng, Ping-Kuo
;
電控工程研究所
The objective of this paper is to develop an ultra-low-power video compression processor for capsule endoscope to lower the RF transmitter bandwidth. In applications of capsule endoscope, it is imperative to consider battery life and performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are also many fast video compression algorithms for reducing computation load; however, they may result in distortion of original image. A new video compression algorithm for gastrointestinal image based on H.264 Intra-frame encoder and its corresponding VLSI architecture are both proposed for low-power, high bite-rate wireless capsule endoscope. The algorithm exploits the characteristic of gastrointestinal image and H.264 intra-frame prediction technique to reduce computing complexity and save battery power consumption. As the result of implementation, the developed video compressor for 512-by-512 image sensor and 2 Mbits/sec RF transmitter costs 60k gates and consumes 0.9161mW power at 2 frames/sec while the average compression rate can be as low as 82%.
A Modified H.264 Intra-frame Video Encoder for Capsule Endoscope
(2008)
Dung, Lan-Rong
;
Wu, Yin-Yi
;
Lai, Hsin-Cheng
;
Weng, Ping-Kuo
;
電控工程研究所
The objective of this paper is to develop an ultra-low-power video compression processor for capsule endoscope to lower the RF transmitter bandwidth. In applications of capsule endoscope, it is imperative to consider battery life and performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are also many fast video compression algorithms for reducing computation load; however, they may result in distortion of original image. A new video compression algorithm for gastrointestinal image based on H.264 Intra-frame encoder and its corresponding VLSI architecture are both proposed for low-power, high bite-rate wireless capsule endoscope. The algorithm exploits the characteristic of gastrointestinal image and H.264 intra-frame prediction technique to reduce computing complexity and save battery power consumption. As the result of implementation, the developed video compressor for 512-by-512 image sensor and 2 Mbits/sec RF transmitter costs 60k gates and consumes 0.9161mW power at 2 frames/sec while the average compression rate can be as low as 82%.
A Modified H.264 Intra-frame Video Encoder for Capsule Endoscope
(2008)
Dung, Lan-Rong
;
Wu, Yin-Yi
;
Lai, Hsin-Cheng
;
Weng, Ping-Kuo
;
電控工程研究所
The objective of this paper is to develop an ultra-low-power video compression processor for capsule endoscope to lower the RF transmitter bandwidth. In applications of capsule endoscope, it is imperative to consider battery life and performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are also many fast video compression algorithms for reducing computation load; however, they may result in distortion of original image. A new video compression algorithm for gastrointestinal image based on H.264 Intra-frame encoder and its corresponding VLSI architecture are both proposed for low-power, high bite-rate wireless capsule endoscope. The algorithm exploits the characteristic of gastrointestinal image and H.264 intra-frame prediction technique to reduce computing complexity and save battery power consumption. As the result of implementation, the developed video compressor for 512-by-512 image sensor and 2 Mbits/sec RF transmitter costs 60k gates and consumes 0.9161mW power at 2 frames/sec while the average compression rate can be as low as 82%.
A Motion-robust Contactless Photoplethysmography Using Chrominance and Adaptive Filtering
(2015-01-01)
Huang, Ren-You
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Dung, Lan-Rong
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電控工程研究所
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Institute of Electrical and Control Engineering
Recently, the camera-based photoplethysmography (PPG) techniques have been proposed for heart rate measurement due to the contactless and low-cost features. However, the previous works showed limited success for moving subjects, especially when the signal of skin color changes rendered by vigorous motion is in the same frequency band as that by blood volume variations. This paper proposed a motion robust, contactless method for measuring heart rate when the human subject is exercising on some fitness machines, e.g. treadmill or stepper. The proposed method combines the chrominance-based method with adaptive filtering to make the heart rate measurement robust to vigorous motions on fitness machine while estimating the heart rate in frequency domain. To demonstrate the performance of heart rate measurement, we taped a video sequence of treadmill exercise with various motion themes. As shown in experimental results on the video sequence, our method can significantly improve the measurement accuracy from 61%
A NAND flash memory controller for SD/MMC flash memory card
(2007-02-01)
Lin, Chuan-Sheng
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Dung, Lan-Rong
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交大名義發表
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電控工程研究所
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National Chiao Tung University
In this paper, a novel NAND flash memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the flash memory chip during the card production stage, the function for supporting various kinds of NAND flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) flash memory card controller chip was designed and implemented with UMC 0.18 mu m CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.
A NAND flash memory controller for SD/MMC flash memory card
(2006)
Lin, Chuan-Sheng
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Chen, Kuang-Yuan
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Wang, Yu-Hsian
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Dung, Lan-Rong
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電控工程研究所
In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit Parallel BCH ECC code was designed for correcting the random bit errors of the Rash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (In System Programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC flash memory card controller chip was designed and implemented with UMC 0.18 um CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.
A parallel-in folding technique for high-order FIR filter implementation
(2006-12-01)
Dung, Lan-Rong
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Yang, Hsueh-Chih
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper presents a hardware-efficient folding technique for high-order FIR filtering while considering the tradeoff between the number of processing elements and throughput rate. Given the throughput rate, one can always employ the minimum number of processing elements for saving the implementation cost and figure out a folded architecture. However, applying inefficient folding techniques may result in costly switches and registers. Therefore, our work intends to evaluate the efficiency for folding techniques in terms of the number of registers, and the power dissipation of registers. As shown in the estimation results, while comparing with the published folded architectures under the same throughput rate, the proposed folding technique can turn out less power dissipation and low hardware complexity than the others. The proposed design has been implemented using TSMC 0.18 mu m 1P6M technology. As seen in the post-layout simulation, our design can meet the requirement of IS-95 WCDMA pulse shaping FIR filter while the power consumption can be as low as 16.66 mW.
A power-aware motion estimation architecture using content-based subsampling
(2006-07-01)
Cheng, Hsien-Wen
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Dung, Lan-Rong
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper presents a novel power-aware motion estimation architecture for battery-powered multimedia devices. As the battery status changes, the proposed architecture adaptively performs graceful tradeoffs between power consumption and compression quality. The tradeoffs are considered to be graceful in that the proposed architecture is scalable with changing conditions and the compression quality is slightly degraded as the available energy is depleted. The key to such tradeoffs lies in a content-based subsample algorithm, first proposed in this paper. As the available energy decreases, the algorithm raises the subsample rate for maximizing the battery lifetime. Differently from the existing subsample algorithms, the content-based algorithm first extracts edge pixels from a macro-block and then subsamples the remaining low-frequency part. By doing so, we can alleviate the aliasing problem and, thus, limit the quality degradation as the subsample rate increases. Given a power consumption mode, the proposed architecture first performs edge extraction to generate a turn-off mask and then uses the turn-off mask to reduce the switch activities of processing elements (PEs) in a semi-systolic array. The reduction of switch activities results in significant power consumption savings. To achieve a high degree of scalability and qualified power-awareness, we use an adaptive control mechanism to set the threshold value for edge determination and make the reduction of switch activities rather stationary. As shown by experimental results, the architecture can dynamically operate in different power consumption modes with little quality degradation according to the remaining capacity of the battery pack while the power overhead of edge extraction is kept under 0.8%.
A Robust, Intelligent CC-CV Fast Charger for Aging Lithium Batteries
(2016)
Dung, Lan-Rong
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Chen, Chieh-En
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Yuan, Hsiang-Fu
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電機工程學系
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電控工程研究所
This paper proposes a robust, intelligent constant current-constant voltage (CC-CV) charger for fast charging an aging Lithium-ion battery. Increasing the charging current in the CC regime cannot guarantee the short charging time, so an optimal charging current exists in the CC-CV method. The optimal charging current changes with battery degradation, so this paper figures out a way to find the optimal charging current by applying direct current internal resistance (DCIR) tests before the CC-CV charging method. The experiment results show that the proposed charger can adjust the optimal current based on battery state-of-health (SOH). The charging time has a 6.5% improvement when it is compared to a standard CC-CV fast charger.
A Subsample-Based Low-Power Image Compressor for Capsule Gastrointestinal Endoscopy
(2011)
Lin, Meng-Chun
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Dung, Lan-Rong
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電控工程研究所
;
Institute of Electrical and Control Engineering
In the design of capsule endoscope, the trade-offs between battery-life and video-quality is imperative. Typically, the resolution of capsule gastrointestinal (GI) image is limited for the power consumption and bandwidth of RF transmitter. Many fast compression algorithms for reducing computation load; however, they may result in a distortion of the original image, which is not suitable for the use of medical care. This paper presents a novel image compression for capsule gastrointestinal endoscopy, called GICam-II, motivated by the reddish feature of GI image. The reddish feature makes the luminance or sharpness of GI image sensitive to the red component as well as the green component. We focus on a series of mathematical statistics to systematically analyze the color sensitivity in GI images from the RGB color space domain to the two-dimensional discrete-cosine-transform spatial frequency domain. To reduce the compressed image size, GICam-II downsamples the blue component without essential loss of image detail and also subsamples the green component from the Bayer-patterned image. From experimental results, the GICam-II can significantly save the power consumption by 38.5% when compared with previous one and 98.95% when compared with JPEG compression, while the average peak signal-to-noise ratio of luminance (PSNRY) is 40.73 dB.
A subsample-based motion estimation for quality-stationary video coding
(2006)
Lin, Meng-Chun
;
Dung, Lan-Rong
;
Lin, Hsuan-Po
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交大名義發表
;
National Chiao Tung University
The block-matching motion estimation has been aggressively developed for years. Many papers have presented fast block-matching algorithms (FBMAs) for the reduction of computation complexity. Nevertheless, their results, in terms of video quality and bitrate, are rather content-varying. Very few FBMAs can result in stationary or quasi-stationary video quality or bitrate for different types of video content. This paper presents a content-motion-aware motion estimation for quality-stationary video coding. By adaptively specifying the subsample ratio, the proposed algorithm can adjust the computational load for acceptable quality loss under the rate control mechanism. As the simulation result, the proposed algorithm can produce stationary quality at the PSNR of 036 dB for a given bitrate while saving about 69.6% power consumption.
A VLSI Implementation of Variation-Free PUF-based Processor for RFID Applications
(2013-01-01)
Dung, Lan-Rong
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Chen, Chang-Ting
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
The Physically Unclonable Function (PUF) has been presented to defend physical attacks for RFID authentication. The silicon PUF employs difference of gate and wire delays on silicon chip to protect hardware copies of RFID. Because of the process variation in IC manufacturing, each silicon chip has different delays for gates and wires and, thus, the PUF-based encryption on each chip has different output even though the logic design is the same as the others. Research has been focusing on low-cost PUF implementation with a chain of logic blocks. However, some operating variations such as power-supply voltage and temperature variations might cause the failure of authentication. This paper presents a variation-free PUF-based processor with error control coding (ECC) technology. We used the ECC encoder to generate parity code for variation compensation. Therefore, our chip can generate a variation-free PUF encryption for RFID application. The chip is implemented by TSMC 0.18um CMOS process. As shown in the results, the chip area is as small as 0.83 mm<^>2 and its power dissipation is 87 uW.
A VLSI progressive coding for wavelet-based image compression
(2007-05-01)
Chiang, Tsung-Hsi
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Dung, Lan-Rong
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電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new algorithm for progressive image coding, called Tag Setting In Hierarchical Tree (TSIHT). The TSIHT coding can save the memory requirement while keeping the low-bit-rate quality high. The TSIHT algorithm has been implemented onto a chip with 0.35 mu IP4M CMOS technology. The chip can handle 256x256 gray-scale images and the gate count is about 2560 gates within 247500 mu m2 area. The latency of the critical path is 6.32 ns, and the maximum working frequency can be as high as 158 MHz.(1)
A Voltage-Gradient Based Gas Gauge Platform for Lithium-ion Batteries
(2018-01-01)
Dung, Lan-Rong
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Li, Hao-Pin
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交大名義發表
;
National Chiao Tung University
A supplementary compensator for Texas Instruments gauge IC state-of-charge estimation for lithium-ion batteries is proposed and a hardware platform is designed to verify the proposed compensation. A sudden change in TI gauge SOC estimation sometimes happens near the end section of the battery discharge curves. The reason is that there are non-modification regions posed by the gauge due to larger parameter variation caused larger SOC estimation errors. By designing the OCV extraction hardware and find that the difference of slopes has a big drop when approaching to 50% SOC and the value can be identified. The slope of 50% SOC is a fixed value which can be applied to SOC compensation. By analyzing the discharging curves for many vendors' lithium-ion batteries, we find that there are two conditions can be applied to compensate the SOC estimation. One is the specific difference of voltage slopes during discharging and the other is a specific discharging slope when SOC equals 50%. These check points can provide nearly consistent estimation of SOC for batteries with different cycle times and different ambient temperatures. An add-on platform is designed with the embedded voltage-gradient checkpoint and EMF table and the experimental results show that the SOC estimation accuracy is improved. The accuracy of SOC estimation with the help of the proposed compensation is increasing up to 11% under different variant current profiles.