Browsing by Author "Fan, CL"

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A novel two-step annealing technique for the fabrication of high performance low temperature poly-Si TFTs
(2003-08-01)
Fan, CL
;
Chen, MC
;
Chang, Y
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low temperature processed (LTP) poly-Si thin film transistors (TFTs) fabricated with a poly-Si film crystallized by a novel two-step annealing (NTSA) technique were investigated and compared with those using conventional solid phase crystallization (SPC) and excimer laser annealing (ELA) schemes. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 h at 600degreesC) creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSA poly- Si film not only exhibit a better performance but also significantly shorten the crystallization time as compared to those fabricated using the conventional SPC (about 20 h or longer at 600degreesC). In addition, the uniformity of the device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. (C) 2003 The Electrochemical Society.
Correlation between electrical characteristics and Oxide/Polysilicon interface morphology for excimer-laser-annealed poly-Si TFTs
(2002-10-01)
Fan, CL
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work investigates the correlation between electrical characteristics and gate-oxide/polysilicon interface morphology for excimer-laser-annealed (ELA) poly-Si thin-film transistors (TFTs). The main feature of ELA poly-Si films is protrusion at grain boundaries that makes the film surface appear very rough. The surface roughness increases with increasing laser energy density and causes degradation of off-current and reliability for the ELA poly-Si TFTs. This degradation of the off-current is attributed to the lower channel resistance due to the increase in crystallinity of the poly-Si layer and the enhancement of localized electric field arising from the protrusions at the grain boundaries. In addition, the increase of localized electric field also degrades device reliability. Passivation of gate oxide/poly-Si channel by NH3-plasma treatment was found to be favorable in improving the performance and reliability of the ELA poly-Si TFTs. (C) 2002 The Electrochemical Society.
Effects of N2O plasma treatment on the performance of excimer-laser-annealed polycrystalline silicon thin film transistors
(2002-09-01)
Fan, CL
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of NO plasma treatment on the performance of excimer-laser-annealed (ELA) polycrystalline silicon thin film transistors (poly-Si TFTs) were investigated. The N2O plasma treatment was conducted following, the deposition of the low-temperature gate oxide. resulting in all Obvious improvement in the performance of the ELA poly-Si TFTs. This improvement is presumably due to the smoothed oxide/poly-Si interface. the improved gate-oxide quality. and the reduced trap states at the interface and in the poly-Si channel. resulting from the incorporation and passivation reaction of the N2O-plasma-generated nitrogen and oxygen radicals. Moreover, the NO plasma treatment also improved the quality of the ELA poly-Si TFTs under dc voltage stress.
Fabrication of high performance low-temperature poly-Si thin-film transistors using a modulated process
(2002-04-01)
Fan, CL
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A modulated process (MP) for the fabrication of low temperature processed (LTP) polysilicon thin-film transistors (poly-Si TFTs) using fewer processing steps but resulting in improved performance is investigated in this study. The modulated process is characterized by combining the solid-phase crystallization (SPC) step and the implant annealing into a single annealing step processed after the source/drain implantation. This is to say that the processing step of SPC is omitted, such that the SPC and implant annealing are conducted simultaneously. In this way, the process time is substantially shortened and the device performance is significantly improved. The improvement of device performance is presumably attributed to the larger poly-Si grain in the channel region processed by the MP scheme. In addition, the MP samples have a better NH3-plasma passivation efficiency than the conventional process (CP) samples; this also implies that the MP samples contain larger grains in the channel regions than the CP samples. The electrical stress-induced degradation of device characteristics for the NH3-plasma passivated MP samples is attributed to the carrier-induced metastable defects in the channel region. (C) 2002 The Electrochemical Society.
Investigation of silicon oxide films prepared by room-temperature ion plating
(1998-01-15)
Yeh, CF
;
Chen, TJ
;
Fan, CL
;
Kao, JS
;
電子工程學系及電子研究所
To develop excellent silicon oxide film using low temperature method, ion plating (IP) oxide is investigated. Physicochemical characterizations of the IP oxide are studied using ellipsometry, Fourier transform infrared spectrometry, and P-etch rate measurement. The IP oxide is a high-density dielectric with strained bonds. Electrical characterizations are also analyzed using capacitance-voltage and current-voltage techniques through metal-oxide-semiconductor capacitors. The IP oxide has a low leakage current, a high breakdown field, and low interface state density. In addition, IP oxide annealed in N-2 ambient is also studied. After high-temperature annealing, the characteristics of IP oxide become comparable to those of thermal oxide. The novel oxide him is successfully applied as a gate insulator to low-temperature processed (less than or equal to 620 degrees C) polysilicon thin-film transistors. (C) 1998 American Institute of Physics.
Low temperature processed poly-Si thin-film transistors with thinner LPD-SiO2 as gate insulator and its reliability
(1995)
Fan, CL
;
Yeh, CF
;
Tsai, HK
;
Lur, W
;
Yen, PW
Low-temperature-processed polycrystalline silicon thin-film transistors using a new two-step crystallization technique
(2003-10-01)
Fan, CL
;
Chen, MC
;
Chang, Y
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low-temperature-processed (LTP) Polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated with a poly-Si film crystallized by a new two-step crystallization (NTSC) technique were investigated. The NTSC is characterized by the combination of excimer-laser-induced formation of nucleation centers and short-time low- temperature furnace annealing to create clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSC poly-Si film not only exhibit better performance but also significantly shorten the crystallization time (about 6 h at 600degreesC) as compared to those fabricated using conventional solid phase crystallization (about 20 h or longer at 600degreesC).
Performance improvement of excimer laser annealed poly-Si TFTs using fluorine ion implantation
(2002-08-01)
Fan, CL
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Significant improvement of device performance was observed for the excimer laser annealed (ELA) poly-Si thin film transistors (TFTs) by the incorporation of fluorine atoms using the ion implantation technique. This is presumably due to the relaxation of mechanical stress at the poly-Si/buffer-oxide interface and the passivation of trap-states in the poly-Si channel region and at the gate-oxide/poly-Si interface. We achieved high performance ELA poly-Si TFTs with a very low off-current of similar to0.26 pA/mum and a very high On/Off current ratio of about 10(8). Moreover, the fluorine ion implantation also greatly improved the reliability of the ELA poly-Si TFTs with respect to the hot-carrier stress, presumably due to the formation of strong Si-F bonds. (C) 2002 The Electrochemical Society.