Browsing by Author "Fan, Cheng-Han"

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Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding
(2013)
Chang, Yao-Jen
;
Ko, Cheng-Ta
;
Hsiao, Zhi-Cheng
;
Chiang, Cheng-Hao
;
Fu, Huan-Chun
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250 degrees C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Interdiffusion of Cu-Sn System with Ni Ultra-thin Buffer Layer and Material Analysis of IMC Growth Mechanism
(2014)
Fan, Cheng-Han
;
Chang, Yao-Jen
;
Chou, Yi-Chia
;
Chen, Kuan-Neng
;
電子物理學系
In this paper, Ni ultra-thin diffusion buffer layer between Cu/Sn is inserted to suppress the IMC (n-phase) inter-diffusion reaction. We analogy the bonding condition by using single side Cu/Ni buffer layer/Sn structure. The inter-diffusion behaviors and IMC growth are investigated under the same thermal budget of bonding temperature during the heating step. Cu/Sn IMC formation behavior with Ni buffer layer is summarized by the SEM inspection. In the results of different Ni buffer layers (t(Ni) = 0, 50, 100, 150 angstrom) and thermal durations (0 to 60 sec), Ni buffer layer insertion can effectively reduce Cu/Sn IMC thickness. In addition, rapid growth of similar to 1.5 mu m Cu/Sn IMC thickness at 250 degrees C for only 10 sec is discovered. As results, 100 angstrom Ni buffer layer is necessary to apply as the Cu/Sn system enters the submicron pad bonding interconnects.
Study of Self-Assembly Technology for 3D Integration Applications
(2015)
Chang, Hsiao-Chun
;
Fan, Cheng-Han
;
Chou, Yi-Chia
;
Chen, Kuan-Neng
;
電子物理學系
In this paper, the self-assembly technology is investigated in order to apply on the alignment method to achieve rapid and accurate multichip-to-wafer stacking. By virtue of distinct liquid surface tensions between hydrophilic and hydrophobic materials, the hydrophilic chips can be self-aligned to the hydrophilic substrate which is defined by the surrounding hydrophobic substrate. The surface quality of hydrophobic film with self-assembled monolayers (SAMs) based on self-assembled mechanism strongly affects the performance of alignment. The surface quality of SAMs film which depends on experimental parameters such as dip-coating time and heating time is critical to determine the accuracy of alignment. Moreover, the chip shape and size also have an impact on the alignment accuracy. By improving the misalignment, a good design by the self-assembled mechanism for the self-alignment method can be applied in the bonding technology.