Browsing by Author "Fan, Chi-Wei"

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A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz
(2011-12-01)
Tseng, Wei-Hsin
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Fan, Chi-Wei
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 x 750 mu m(2). It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
ADC Clock Jitter Measurement and Correction Using a Stochastic TDC
(2010)
Fan, Chi-Wei
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology, the TDC consists of 127 timing comparators. The proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.
Jitter Measurement and Compensation for Analog-to-Digital Converters
(2009-11-01)
Fan, Chi-Wei
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Clock jitter is measured and digitized by a stochastic time-to-digital converter (TDC). This jitter information is used to compensate the sampling error of an analog-to-digital converter (ADC) caused by the clock jitter. The following two system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. TDC calibrations for both scenarios are proposed. The calibrations are based on signal reconstruction and can be performed in the background. Both theoretical analyses and system simulations are provided to verify the proposed jitter compensation and TDC calibration techniques.