Browsing by Author "Fan, Mei-Lian"

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Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
(2014-11-01)
Lin, Chun-Yu
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Fan, Mei-Lian
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
ESD Protection Design for Gigahertz Differential LNA in a 65-nm CMOS Process
(2015)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
Fu, Wei-Hao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The electrostatic discharge (ESD) immunity test for EMC was one important reliability regulation. The turn-on-efficient on-chip ESD protection circuit is required to clamp the overstress voltage. A new design of ESD protection diodes with embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential low-noise amplifier (LNA). Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
(2014)
Lin, Chun-Yu
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Fan, Mei-Lian
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Ker, Ming-Dou
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Chu, Li-Wei
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Tseng, Jen-Chou
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
Optimization on Layout Style of Diode Stackup for On-Chip ESD Protection
(2014-06-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V-DD or lower than V-SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.