Browsing by Author "Fan, Ming-Long"

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A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits
(2012)
Pao, Chia-Hao
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Fan, Ming-Long
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Tsai, Ming-Fu
;
Chen, Yin-Nien
;
Hu, Vita Pi-Ho
We present a comprehensive comparative analysis of FinFET and Trigate device characteristics, 6T SRAM stability and logic circuits. The impact of intrinsic random device variations, including fin Line Edge Roughness (LER), Work Function Variation (WFV) and fin width scaling on FinFET and Trigate device Subthreshold Slope (S. S.), V-T, 6T SRAM Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are investigated and compared by using 3D atomistic TCAD simulation. The results indicate that Trigate device shows slightly better variability control under the same electrical width and fin width (10nm and 7nm) considering fin LER and WFV. Next, we investigate the impact of single charged trap induced Random Telegraph Noise (RTN) on FinFET and Trigate device characteristics, 6T SRAM and logic circuits. The top-gate and the lower fin height of Trigate device under the same electrical width and fin width cause the current density to concentrate close to the bottom of the fin, resulting in stronger dependence on the location of the trap, larger RTN Delta I-D/I-D amplitude and larger Delta V-T with a trap placed at the worst position under fin LER and WFV. The impact of RTN trapping/detrapping on 6T SRAM RSNM, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. With degreasing supply voltage, the RTN degradation of Trigate SRAM RSNM and logic circuits become larger compared with the FinFET counterparts.
Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist
(2015-06-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes the impacts of read-assist and write-assist circuits on GeOI FinFET 6T SRAM cells considering intrinsic random variations, process corner, and temperature variation. The word-line under-drive (WLUD) read-assist is more efficient to improve the read static noise margin and read V-MIN of fast-N slow-P corner GeOI FinFET SRAM cells compared with the Silicon-On-Insulator (SOI) counterparts. GeOI FinFET SRAM cells with WLUD show less cell read access-time degradation compared with the SOI counterparts at both 25 degrees C and 125 degrees C. With transient voltage collapse (TVC) write-assist, the write-ability and variation tolerance of GeOI and SOI FinFET SRAM cells are improved. The temperature dependence of data retention time is different between the GeOI and SOI FinFET SRAM cells. The maximum TVC write-assist pulsewidth constrained by the data retention failure is smaller in GeOI FinFET SRAMs at 25 degrees C and becomes comparable at 125 degrees C compared with the SOI FinFET SRAMs.
Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
(2013)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
Analysis of Germanium FinFET on SOI substrate (GeOI FinFET) at device and circuit level is presented. The amplified Band-To-Band Tunneling (BTBT) leakage of GeOI FinFETs is observed due to the parasitic bipolar effect, and the BTBT induced parasitic bipolar leakage dominates the leakage current of GeOI FinFET. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI FinFET logic circuits and SRAMs. Drain-side underlap is the most effective way for leakage reduction of GeOI FinFETs, while increasing channel doping is the least effective way for leakage reduction of GeOI FinFETs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
(2013-06-01)
Fan, Ming-Long
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Hu, Vita Pi-Ho
;
Chen, Yin-Nein
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Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of a single acceptor-type and donor-type interface trap induced random telegraph noise (RTN) on tunnel FET (TFET) devices and its interaction with work function variation (WFV) using atomistic 3-D TCAD simulations. Significant RTN amplitude (Delta I-D/I-D) is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. In addition, several device design parameters that can be used to improve TFET subthreshold characteristics (thinner equivalent oxide thickness or longer L-eff) are found to increase the susceptibility to RTN. Our results indicate that under WFV, TFET exhibits weaker correlation between I-ON and I-OFF than that in the conventional MOSFET counterpart. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of the trap and the composition/orientation of metal-gate grain.
Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated.
"Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits"
(2012-08-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
"This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing (S.S.) and comparable trap-induced V-T shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V-dd), the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way NAND, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause similar to 24%-27% and similar to 13%-15% variations in leakage and delay at V-dd = 0.4 V, respectively, for the logic circuits evaluated."
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking
(2012-02-01)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
This letter indicates that the ultra-thin-body (UTB) germanium-on-insulator (GeOI) MOSFETs preserve the leakage reduction property of stacking devices, while the band-to-band-tunneling leakage of bulk Ge-channel devices cannot be reduced by stacking transistors. The seemingly contradictory behavior of the stack-effect factors is explained by the difference in the flows of band-to-band-tunneling hole fluxes for UTB GeOI and bulk Ge-channel devices and validated by TCAD mixed-mode simulations. At 300 K, the stack-effect factors of UTB GeOI MOSFETs range from 6.8 to 40 (N = 2) and from 12 to 142 (N = 3) at Vdd = 0.5-1V. As the temperature increases or Vdd decreases, the stack-effect factor for UTB GeOI devices decreases, while the stack-effect factor for bulk Ge-channel MOSFETs increases, because the subthreshold leakage current becomes more significant at higher temperature or lower voltage with respect to the band-to-band-tunneling leakage current.
Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
(2013-10-01)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
;
電子工程學系及電子研究所
We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed.
Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based Approach
(2011-03-01)
Fan, Ming-Long
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Wu, Yu-Sheng
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Hu, Vita Pi-Ho
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Hsieh, Chien-Yu
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Su, Pin
This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal READ static noise margin (RSNM) because of the reduced READ disturb. For 4T cells, the nearly ideal values of V(write, 0) and V(write, 1) guarantee the positive nominal WRITE static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between WRITE time (for selected cells) and WRITE disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger mu RSNM and a slightly worse sigma RSNM shows a comparable mu/sigma ratio in RSNM with the 6T cell. Furthermore, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced sigma RSNM can outperform the 6T cell. For WRITE operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between WRITE time and WRITE disturb needs to be carefully examined to ensure an adequate margin considering device variability.
Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature Sensitivity
(2011)
Hu, Vita Pi-Ho
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
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電子工程學系及電子研究所
A comprehensive comparative analysis of leakage-delay, stability and variability of GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts is presented. The UTB GeOI circuits show better power-performance than the bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better mu RSNM/sigma RSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V.
Design and Analysis of Robust Tunneling FET SRAM
(2013-03-01)
Chen, Yin-Nien
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Fan, Ming-Long
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Hu, Vita Pi-Ho
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Su, Pin
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Chuang, Ching-Te
With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.
Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM
(2009)
Hu, Vita Pi-Ho
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Wu, Yu-Sheng
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Fan, Ming-Long
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Su, Pin
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Chuang, Ching-Te
This paper analyzes the stability, margin, and performance of Ultra-Thin-Body (UTB) SOI 6T/8T SRAM cells operating in subthreshold region. An analytical SNM model for UTB SOI 6T/8T SRAM cells operating in the subthreshold region is presented to investigate the Read SNM (RSNM) and Write SNM (WSNM). Our results indicate that back-gating technique is more effective in the subthreshold region than in the superthreshold region for improving RSNM and WSNM. The UTB SOI 6T SRAM cell with back-gating technique to increase the strength of the pull-up transistors and decrease the strength of the pass-gate transistors shows comparable RSNM in the subthreshold region with the 10T bulk subthreshold SRAM cell and an improvement in RSNM variation. Due to better electrostatic integrity, back-gating technique (pull-up PFET with positive back-gate bias, pull-down/pass-gate NFET's with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in the subthreshold region. Mixed-mode device/circuit simulations show that 6T/8T UTB SOI SRAMs operating in the subthreshold region can meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.
Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs
(2013)
Tsai, Ming-Fu
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Fan, Ming-Long
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Pao, Chia-Hao
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Chen, Yin-Nien
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Hu, Vita Pi-Ho
This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at V-DD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising V-trip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.
Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates
(2013)
Hu, Vita Pi-Ho
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Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
A comparative analysis of Germanium-on-Insulator FinFET (GeOl FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOl and Ge bulk FinFET circuits and SRAMs. An optimum asymmetrie underlap design in SRAM using asymmetrie underlap pull-up and access transistors (PUAX-asym) is proposed. GeOl and Ge bulk FinFETs with asymmetrie underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
(2016-02-01)
Yu, Chang-Hung
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Fan, Ming-Long
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Yu, Kuan-Chin
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Hu, Vita Pi-Ho
;
Su, Pin
For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications.
Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
(2016-03-01)
Yu, Kuan-Chin
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Fan, Ming-Long
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Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixed-mode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.
Evaluation of Read-and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells
(2014-01-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電機工程學系
This paper evaluates the impacts of Read- and Write-Assist circuits on the GeOI FinFET 6T SRAM cells compared with the SOI counterparts. The Word-Line Under-Drive (WLUD) Read-Assist is more efficient to improve the Read Static Noise Margin (RSNM) and Read VMIN of FNSP GeOI FinFET SRAM cells compared with the SOI counterparts. GeOI FinFET SRAM cells with WLUD show smaller cell Read accesstime compared with the SOI FinFET SRAM cells at both 25 degrees C and 125 degrees C. Negative Bit-Line (NBL) Write-Assist is more efficient to improve the Write Static Noise Margin (WSNM) than VCS (cell supply) lowering for both GeOI and SOI FinFET SRAM cells. NBL Write-Assist shows larger WSNM improvement for GeOI FinFET SRAM cells than the SOI counterparts at 125 degrees C.
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
(2014-12-01)
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, V-min and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across V-DD = 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation.