Browsing by Author "Fan, Y. C."

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A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Chang, K. Y.
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Liu, C. H.
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Chien, C. H.
A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I-on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I-on, comparable to those of LP planar CMOS devices, 0.1 nA/um of I-off, while excellent S.S.(<10mV/dec) at V-dd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Liu, C. H.
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Chung, Steve S.
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Huang, R. M.
A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.