Browsing by Author "Fang, SJ"

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Reactive bandwidth arbitration for priority and multicasting control in ATM switching
(1997)
Fang, SJ
;
Lin, YS
;
Yang, SC
;
Shung, CB
;
交大名義發表
A new service scheduling scheme, reactive bandwidth arbitration (RBA), is proposed as an effective way to arbitrate the contention among priority classes or between unicast and multicast services in ATM switching. The RBA scheme integrates two previously proposed concepts: bandwidth allocation and reactive arbitration. In, RBA, guaranteed bandwidth is allocated to a connection at call setup based on the traffic characteristics and service requirements, while the arbitration of cell delivery takes into account the queue status to react to traffic fluctuation. Through simulation, we found that by bandwidth allocation, a set of queue threshold levels can be obtained to provide a good approximation to the desired delay performance. Furthermore, around this initial configuration, a linear relationship between the queue threshold and the resulting delay performance car be established to fine-tune the configuration parameters for the desired delay performance. Similar effects were observed as the RBA scheme was applied to arbitrate the contention between unicast and multicast connections in a shared buffer ATM switch. The proposed RBA scheme was incorporated in a queue manager chip for an 8 X 8 shored buffer ATM switch with four priority classes per port and link rate at 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) and operates at 25 MHz.
VLSI design of a priority arbitrator for shared buffer ATM switches
(1997)
Lin, YS
;
Yang, SC
;
Fang, SJ
;
Shung, CB
;
交大名義發表
Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA): and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8x8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) using 0.6 mu m CMOS technology.