Browsing by Author "Fang, Wai-Chi"

Now showing 1 - 20 of 114

A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
(2009)
Chen, Chih-Lung
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Lin, Kao-Shou
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Chang, Hsie-Chia
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Fang, Wai-Chi
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Lee, Chen-Yi
In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
A 16 Channel Real-Time EEG Processing Based on ORICA Algorithm using 28nm CMOS Technology
(2018-01-01)
Wang, Kai-Yen
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Ho, Yun-Lung
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Huang, Yu-De
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Fang, Wai-Chi
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交大名義發表
In this paper, we propose a system-on-chip(SOC) design of highly effective multi-channel real-time EEG signal processing system based on Online-Recursive Independent Component Analysis (ORICA) algorithm implemented using TSMC's 28nm CMOS technology. In this chip, concepts of system-on-chip (SOC) design and effective system integration technique are well-combined together to realize a highly miniaturized realtime EEG processing system.. The core area and total power consumption of the chip are respectively 1246* 1246 mu m2 and 25.03mW. The chip operations were validated by ADVANTEST V93000 PS1600 and the results obtained match with the software simulation. The average correlation coefficient between original source signals and extracted ORICA signals reaches 0.9572. Eye blink artifact, and facial muscle artifact will be removed automatically. Producing a pure EEG signal is beneficial for realtime data analysis; therefore, this chip design can enhance the reliability and feasibility of EEG-related applications, such as BCI, medical diagnosis and depth of anesthesia detection.
A Brain-Computer Interface with Real-Time Independent Component Analysis for Biomedical Applications
(2012)
Hsieh, Zong-Han
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Fang, Wai-Chi
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Jung, Tzyy-Ping
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a brain-computer interface with real-time independent component analysis for biomedical applications. EEG-based BCI technology using cell-phone and Bluetooth transmission of bio-signals has been established in previous studies, and experimental results show that subjects should avoid eye blink who are under test to increase the accuracy. In order to enhance the dialing system, the authors integrate a real-time ICA chip to artifacts arising from eye blinking. The designed system enables the acquisition and subsequent ICA elaboration signals in real-time, the result shows suitable for BCI applications. The efficiency of the implemented technique has been experimentally demonstrated.
A Customized Convolutional Neural Network Design Using Improved Softmax Layer for Real-time Human Emotion Recognition
(2019-01-01)
Wang, Kai-Yen
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Huang, Yu-De
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Ho, Yun-Lung
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Fang, Wai-Chi
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電子工程學系及電子研究所
This paper proposes an improved softmax layer algorithm and hardware implementation, which is applicable to an effective convolutional neural network of EEG-based real-time human emotion recognition. Compared with the general softmax layer, this hardware design adds threshold layers to accelerate the training speed and replace the Euler's base value with a dynamic base value to improve the network accuracy. This work also shows a hardware-friendly way to implement batch normalization layer on chip. Using the EEG emotion DEAP[7] database, the maximum and mean classification accuracy were achieved as 96.03% and 83.88% respectively. In this work, the usage of improved softmax layer can save up to 15% of training model convergence time and also increase by 3 to 5% the average accuracy.
A Data Detection Scheme for Single-Carrier Block Transmission Using Sphere Decoding Algorithm
(2010)
Lin, Ying-Tsung
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Kuo, Chia-Hsun
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Chen, Sau-Gee
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Fang, Wai-Chi
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電子工程學系及電子研究所
In this paper, an efficient sphere decoding algorithm (SDA) applied to solve the inter-symbol-interference (ISI) data detection problem is proposed. This proposed algorithm takes advantages of the SDA to obtain the solution close to ML solution with the simplified K-best tree search method for the ISI data detection under ISI effect. Compared with the frequency-domain MMSE or Zero-Forcing equalization techniques for SCBT (Single-Carrier Block Transmission) systems, this algorithm can perform at least 1.5dB better than frequency-domain equalizers under the environment of randomly generated channel impulse responses.
A Hardware Design for Portable Continuous Wave Diffuse Optical Tomography
(2010)
Kang, Shih
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Wu, Shih-Yang
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Fu, Chih-Chung
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Chua, Ericson
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Hsu, Yuan-Huang
In recent years, the rapid development of diffuse optical tomography (DOT) technology has made possible many successful applications in the field of biomedicine, such as breast cancer detection and observation of oxygenated hemoglobin distribution in the brain. In this work, we build an inexpensive and portable real-time continuous wave near-infrared (CW-NIR) DOT system hardware suitable for use in system on a chip (SOC) applications. With greatly reduced system volume, the system can pave the way for practical developments in the clinical setting. The proposed system processes digitized biomedical signals acquired from a front-end sensor circuit, and can operate in either continuous or discontinuous mode according to user settings. Finally, we demonstrate the improvements in image reconstruction associated with the two-dimensional (2D) post-processing technique employed in the proposed system.
A Hardware-Efficient VLSI Implementation of a 4-Channel ICA Processor for Biomedical Signal Measurement
(2011)
Chen, Chiu-Kuo
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Chua, Ericson
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Fu, Chih-Chung
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Tseng, Shao-Yen
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Fang, Wai-Chi
This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.
A High Efficiency Hardware Design for Real-Time Continuous Wave Diffuse Optical Tomography
(2013)
Wu, Shih-Yang
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Cheng, Ching-Ju
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Fang, Wai-Chi
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Lin, Frankwell
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Yu, Felix
Diffuse Optical Tomography (DOT) is a novel medical image technology with non-invasive method in the recent years. However, it has not been popular in clinical practice. In this work, a custom signal processing engine for Continuous Wave (CW) DOT is proposed, for the forward and inverse problem in the calculating procedure. To achieve the goals of small hardware size, low power consumption, and popularity, the design applied the Very-large-scale integration (VLSI) concept. In addition, the design is also implemented onto System on a chip (SoC) with a front-end sensor control, wireless communication, and a user friendly interface as a prototype of a health care monitor system. Lastly, we demonstrate a static phantom experiment to verify the functionality of the whole proposed system.
A High-Troughput Radix-4 Log-MAP Decoder With Low Complexity LLR Architecture
(2009)
Chuang, Hsiang-Tsung
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Tseng, Kai-Hsin
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Fang, Wai-Chi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm(2) on UMC 0.13 mu m standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.
A Highly Integrated Biomedical Multiprocessor SoC Design for a Wireless Bedside Monitoring System
(2014-01-01)
Lin, Kuen-Chih
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Liao, Jui-Chieh
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Fang, Wai-Chi
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a highly integrated multiprocessor system-on-chip (SoC) design, enabling real-time processing of multi-biomedical signals in a wireless bedside monitoring system. This system includes a real-time online recursive independent component analysis (ORICA) processor to automatically remove brain electroencephalogram (EEG) artifacts signals, a heart rate variability (HRV) analysis processor for monitoring electrocardiogram (ECG) signals, and a basic biomedical signal processor for monitoring common physiological data such as oxygen saturation, blood pressure, or body temperature. The multiprocessor chip is fabricated using TSMC 90 nm CMOS technology, and occupies a core area of 1,600 x 1,600 um(2). Simulated power consumption is 15.89 mW under the conditions of 1.0V core supply voltage and 64 MHz clock operation frequency.
A Highly Integrated Hardware Design Implemented on FPGA for a Wireless Healthcare Monitoring System
(2014-01-01)
Lin, Kuen-Chih
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Fang, Wai-Chi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we present a highly integrated hardware design providing several biomedical signals processing in a wireless healthcare monitoring system. This system includes a biomedical front-end circuits acquires and digitizes biomedical data such as electroencephalogram (EEG) and electrocardiogram (ECG), a control interface to connect and control the biomedical front-end circuits, a real-time online recursive independent component analysis (ORICA) engine to extract artifacts automatically of brain electroencephalogram signals, a heart rate variability (HRV) analysis engine for processing ECG signals and a display platform to display the physiological data. A commercial Bluetooth module is used to transmit wirelessly between the processor and the display platform. This system can provide several physiological data such as blood pressure, oxygen saturation and body temperature. This hardware design implemented using field-programmable gate array (FPGA) and schedule for fabricated using TSMC 90 nm CMOS technology.
A Highly-Integrated Biomedical Multiprocessor System for Portable Brain-Heart Monitoring
(2011)
Chua, Ericson
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Fang, Wai-Chi
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Chen, Chiu-Kuo
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Fu, Chih Chung
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Tseng, Shao-Yen
In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and a heart rate variability (HRV) analysis processor for monitoring heart electrocardiogram (ECG) signals. The multiprocessor chip implemented in 65nm CMOS technology comprises 368k gates and occupies a core area of 462k mu m(2). Simulated power consumption using a full operation test case reports 3.6mW under the condition of 1.0V core supply voltage and 24MHz clock operating frequency.
A Low Power Independent Component Analysis Processor in 90nm CMOS Technology for EEG Signal Processing Systems
(2011)
Chen, Chiu-Kuo
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Wang, Yi-Yuan
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Hsieh, Zong-Han
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Chua, Ericson
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Fang, Wai-Chi
This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 x 1230 mu m(2).
A Non-Contact ECG Sensing System with Motion Artifact Equalization
(2016-01-01)
Gao, Shanqing
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Huang, Ding-Yu
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Fang, Wai-Chi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an electrocardiograph(ECG) non-contact sensing system that compensates the high-frequency noises and the distortion due to motion artifact via two-channel interleaved electrodes in concert with proportional design and equalization algorithm. Specifically, the equivalent input capacitances of the sensing electrodes are deliberately designed to achieve a fast, low-cost, and real-time compensation signal processing. This proposed system has been implemented with a worst case of 2% unit capacitance mismatch and 25% motion artifact with a normal distribution, where the equalization can still achieve average 98.6% high accuracy.
A Non-Linear Iterative Method for Multi-Layer DOT Sub-Surface Imaging System
(2014-01-01)
Hou, Hsiang-Wen
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Wu, Shih-Yang
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Sun, Hao-Jan
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Fang, Wai-Chi
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分子醫學與生物工程研究所
Diffuse Optical Tomography (DOT) has become an emerging non-invasive technology, and has been widely used in clinical diagnosis. Functional near-infrared (FNIR) is one of the important applications of DOT. However, FNIR is used to reconstruct two-dimensional (2D) images for the sake of good spatial and temporal resolution. In this paper we propose a multiple-input and multiple-output (MIMO) based data extraction algorithm method in order to increase the spatial and temporal resolution. The non-linear iterative method is used to reconstruct better resolution images layer by layer. In terms of theory, the simulation results and original images are nearly identical. The proposed reconstruction method performs good spatial resolution, and has a depth resolutions capacity of three layers.
A Novel Handheld Diffuse Optical Spectroscopy System Implementation Based on High-Accuracy Multidimensional Imaging Reconstruction Model for Human Breast Healthcare Applications
(2019-01-01)
Guo, Jia-Jiun
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Wu, Wen-Jun
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Fang, Wai-Chi
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Diffuse Optical Tomography (DOT) is a relatively novel, nonionizing and noninvasive technique for breast tumor imaging. Due to the diffusive nature of light propagation, the inverse problem is highly ill-posed. In this study, we propose the modified Beer-Lambert's law that reduces the number of unknown values to reduce the ill-posedness issue. An integrated mobile DOT system is proposed. The system comprises a front-end circuit and an integrated digital signal processor. The sources and the detectors are distributed hexagonal geometry for increasing the spatial resolution. The processor included the front-end controller, the iteration algorithm engine and wireless communication controller were implemented on FPGA. The functionalities of the proposed system were validated using a breast phantom. Extensive experimental results illustrated to show the performance of the proposed system. The depth of the tumor detected by the system is 20mm.
A Novel Near-Infrared Array Based Arterial Pulse Wave Measurement Method
(2013)
Huang, Wei-Chin
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Hou, Hsiang-Wen
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Cheng, Ching-Ju
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Wu, Shih-Yang
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Chen, Tien-Ho
Recently there have been many studies regarding pulse wave velocity (PWV) produced by near-infrared light. However, these studies have used multiple probes with the synchronization problem. This paper proposed a new detecting method to measure PWV on a radial artery with multiple channels in one front-end sensor array. The system was implemented on a MSP430F169 platform and the PWV result was transmitted by RS232 and displayed on the computer screen after being processed. Finally, the PWV result was measured to validate the functionality of the system.
A Novel Readout Chip with Extendability for Multi-Channel EEG Measurement
(2013-01-01)
Chen, Yi-Chung
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Tsai, Chung-Han
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Hsieh, Zong-Han
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Fang, Wai-Chi
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電子工程學系及電子研究所
This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another adjustable amplification stage and filter are used to process biomedical signals. A 10-bit successive approximation register analog-to-digital converter (SAR-ADC) then links to the back-end for digital signal processing. In the last stage, shift-register pairs are used to transmit data to the next chip and receive data from the previous chip. The shift register design allows the number of channels to be extended. A TSMC 0.18 um CMOS process is used to design the EFRC and it operates with a 1.8 V supply voltage. The results shows that the total power consumption for the EFRC chip is approximately 80.268 uW and the chip area is approximately 944 x 863 um(2).
A Novel Wireless Biomedical Monitoring System with Dedicated FPGA-based ECG Processor
(2012)
Chou, Chia-Ching
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Fang, Wai-Chi
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Huang, Hsiang-Cheh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel portable and wireless biomedical monitoring system featuring on demand wireless data transmission of ECG signals and time-frequency HRV analysis for personal and home healthcare applications is presented in this work. In order to provide comfort and convenience to patients, the device's size, power consumption and portability are of first priority. The ECG processor based on previous hardware design [1] acquires three-channel ECG biomedical raw data through an analog front-end (AFE) circuit, and it measures the time between successive heart beats on lead II as RR intervals for HRV analysis. Functions such as QRS complex peak detection, RR intervals calculation, and time-frequency analysis of HRV have also been developed in hardware. A real-time HRV analysis processor is realized by employing a Lomb periodogram for time-frequency power spectral density (PSD) analysis of the heart rate. The proposed ECG monitoring system has been implemented in Field-Programmable Gate Arrays (FPGA) and it features high integration density, portability, wireless transmission and low cost.
A Pipeline VLSI Design of Fast Singular Value Decomposition Processor for Real-time EEG System Based on On-line Recursive Independent Component Analysis
(2013)
Huang, Kuan-Ju
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Shih, Wei-Yeh
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Chang, Jui Chung
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Feng, Chih Wei
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Fang, Wai-Chi
This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580x580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.