Browsing by Author "Fang, YK"

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Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 mu m CMOSFET with 2-nm thin gate oxide
(2002-12-01)
Yeh, WK
;
Wang, WH
;
Fang, YK
;
Chen, MC
;
Yang, FL
Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BG-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 mum with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 mum FB-SOI pMOSFET is similar to that of the 0.1 mum BG-SOI pMOSFET.
The effect of thermal treatment on device characteristic and reliability for sub-100-nm CMOSFETs
(2004-06-01)
Yeh, WK
;
Fang, YK
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effect of post-thermal annealing after halo implantation on device characteristic and reliability of sub-100-nm CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced degradation. The best result of device performance and reliability was obtained by a post-thermal annealing treatment performed at medium temperatures (e.g., 900 degreesC) for a longer time (>1 min).