Browsing by Author "Fann, YW"

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An intelligent parallel loop scheduling for parallelizing compilers
(2000-03-01)
Fann, YW
;
Yang, CT
;
Tseng, SS
;
Tsai, CJ
;
資訊工程學系
In this paper we propose a knowledge-based approach to solving loop-scheduling problems. A rule-based system, called IPLS, is developed by combining a repertory grid and an attribute ordering table to construct a knowledge base. IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigning parallel loops to multiprocessors to achieve significant speedup. Because more attributes are proposed, the accuracy of selection of an appropriate scheduling method is improved. In addition, the refined IPLS system can automatically adjust the attributes in the knowledge base according to profile information; therefore, IPLS has the capability of feedback learning. The experimental results show that our approach can achieve greater speedup on multiprocessor systems than can others.
IPLS: An intelligent parallel loop scheduling for multiprocessor systems
(1998)
Fann, YW
;
Yang, CT
;
Tsai, CJ
;
Tseng, SS
;
資訊工程學系
In this paper we propose a knowledge-based approach for solving loop-scheduling problems. A rule-based system, called the IPLS, is developed by repertory grid and attribute ordering table to construct the knowledge base. The IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assign parallel loops on multiprocessors for achieving high speedup. In addition, the refined system of IPLS can automatically adjust the attributes in, knowledge base according to profile information; therefore IPLS has the feedback-learning ability.
Using knowledge-based systems for research on parallelizing compilers
(2001-03-01)
Yang, CT
;
Tseng, SS
;
Fann, YW
;
Tsai, TK
;
Hsieh, MH
The main function of parallelizing compilers is to analyze sequential programs, in particular the loop structure, to detect hidden parallelism and automatically restructure sequential programs into parallel subtasks that are executed on a multiprocessor. This article describes the design and implementation of an efficient parallelizing compiler to parallelize loops and achieve high speedup rates on multiprocessor systems. It is well known that the execution efficiency of a loop can be enhanced if the loop is executed in parallel or partially parallel, such as in a DOALL or DOACROSS loop. This article also reviews a practical parallel loop detector (PPD) that is implemented in our PFPC on finding the parallelism in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by verifying array subscripts. In addition, a new model by using knowledge-based approach is proposed to exploit more loop parallelisms in this paper. The knowledge-based approach integrates existing loop transformations and loop scheduling algorithms to make good use of their ability to extract loop parallelisms. Two rule-based systems, called the KPLT and IPLS, are then developed using repertory grid analysis and attribute-ordering tables respectively, to construct the knowledge bases. These systems can choose an appropriate transform and loop schedule, and then apply the resulting methods to perform loop parallelization and obtain a high speedup rate. For example, the IPLS system can choose an appropriate loop schedule for running on multiprocessor systems. Finally, a runtime technique based on the inspector/executor scheme is proposed in this article for finding available parallelism on loops. Our inspector can determine the wavefronts of a loop with any complex indirected array-indexing pattern by building a DEF-USE table. The inspector is fully parallel without any synchronization. Experimental results show that the new method can resolve any complex data dependence patterns where no previous research can. One of the ultimate goals is to construct a high-performance and portable FORTRAN parallelizing compiler on shared-memory multiprocessors. We believe that our research may provide more insight into the development of a highperformance parallelizing compiler Copyright (C) 2001 John Wiley & Sons, Ltd.