Browsing by Author "Fu, Huan-Chun"

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A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
(2014-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Hsiang-Hung
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Lyu, Dian-Rong
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Hsu, Chao-Kai
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Yao-Jen
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Chen, Peng-Shu
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Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration
(2012-03-01)
Chen, Kuan-Neng
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Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Fu, Huan-Chun
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Lo, Wei-Chung
Hybrid bonding, an emerging bonding approach with high yield and reliability, can achieve vertical interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. To develop metal/adhesive hybrid bonding technology, four kinds of polymer materials, BOB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive. The compatibility between each polymer and metal was investigated, and the application range of each material was established thereof. Furthermore, the scheme of Cu-Sn-Cu interconnection hybridized with patterned BCB was designed and evaluated. Two key factors were discussed and optimized to perform the bonding integrity. The evaluation results and successful metal/adhesive hybrid bonding demonstration are disclosed in the paper.
Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding
(2013)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chiang, Cheng-Hao
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Fu, Huan-Chun
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250 degrees C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Process Development and Material Characteristics of TSV-less Interconnection Technology for FOWLP
(2017-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chang, Hsiang-Hung
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Kuo, Tzu-Ying
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Fu, Huan-Chun
Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.