Browsing by Author "Garrido, Mario"

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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
(2014-10-01)
Chen, Sau-Gee
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Huang, Shen-Jui
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Garrido, Mario
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Jou, Shyh-Jye
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電子工程學系及電子研究所
This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
Feedforward FFT Hardware Architectures Based on Rotator Allocation
(2018-02-01)
Garrido, Mario
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Huang, Shen-Jui
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Chen, Sau-Gee
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電機工程學系
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Department of Electrical and Computer Engineering
In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations
(2018-11-01)
Garrido, Mario
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Luisa Lopez-Vallejo, Maria
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Chen, Sau-Gee
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交大名義發表
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National Chiao Tung University
The Serial Commutator FFT
(2016-10)
Garrido, Mario
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Huang, Shen-Jui
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Chen, Sau-Gee
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Gustafsson, Oscar
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電子工程學系及電子研究所
This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.