Browsing by Author "Gu, S. H."

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<bold>Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory</bold>
(2006)
Gu, S. H.
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Li, C. W.
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Wang, Tahui
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Lu, W. P.
;
Chen, K. C.
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations.
Cell Endurance Prediction from a Large-area SONOS Capacitor
(2009)
Lee, C. H.
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Tu, W. H.
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Gu, S. H.
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Wu, C. W.
;
Lin, S. W.
Endurance considerations induced by the degadation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike V-FB (accumulation region), V-T (inversion region) shows a much severe shift. Inter-face state (N-it) is identified as a key factor even when a 2nm bottom oxide is used. Moreover, charge to breakdown (Q(BD)) for an ONO capacitor under positive and negative constant current stress (CCS) is investigated. Our study reveals that QBD of such stacks strongly depends on the top oxide thickness. A field enhancement induced by charges in a trapping nitride layer is the root cause. Based on Weibull statistics, the risk of dielectric breakdown for both blocking layers is then evaluated.
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
;
Gu, S. H.
;
Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Overall Operation Considerations for a SONOS-based Memory
(2009)
Lee, C. H.
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Tu, W. H.
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Chong, L. H.
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Gu, S. H.
;
Chen, K. F.
Erase characteristics of a SONOS-based structure are emulated not only for n(+)-poly and p(+)-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom oxide thickness can be specified with the consideration of the three factors simultaneously. Moreover, it is found that conventional extrapolation methodology is inadequate to predict the lifetime of a TANOS device and tends to under-estimate the tolerable read bias.