Browsing by Author "Guo, J. C."

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65-nm 160-GHz f(T) RF n-MOSFET intrinsic noise extraction and modeling using lossy substrate de-embedding method
(2006-01-01)
Guo, J. C.
;
Lin, Y. M.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A lossy substrate model for accurate simulation of extrinsic noise and a lossy substrate de-embedding method for precise extraction of intrinsic noise have been proven by 80 nm, super-100 GHz f(T) RF nMOS. The method is further applied to 65 nm 160-GHz f(T) nMOS to investigate aggressive gate length scaling effect on RF noise. The extrinsic noise reveals abnormally weak dependence on gate length scaling even with 50 similar to 60% improvement on fT but strong dependence on finger number. The intrinsic noise extracted through lossy substrate de-embedding can consistently reflect the gain in f(T) and weak dependence on finger number. The NFmin at 10 GHz can be suppressed to 0.5dB for 65 nm nMOS corresponding to an optimized drain current, which is around 0.2 dB improvement over 80 nm devices. Noise suppression due to gate length scaling becomes even more significant in higher current region. The noise reduction is attributed to lower noise resistance (R.) and real part of optimum source admittance (Re(Y-opt)). The accurate extraction of intrinsic noise provides useful guideline for RF CMOS device design and optimization in terms of speed, power, and noise.
65-nm 160-GHz f(T) RF n-MOSFET intrinsic noise extraction and modeling using lossy substrate de-embedding method
(2006)
Guo, J. C.
;
Lin, Y. M.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A lossy substrate model for accurate simulation of extrinsic noise and a lossy substrate de-embedding method for precise extraction of intrinsic noise have been proven by 80 nm, super-100 GHz f(T) RF nMOS. The method is further applied to 65 nm 160-GHz f(T) nMOS to investigate aggressive gate length scaling effect on P.F noise. The extrinsic noise reveals abnormally weak dependence on gate length scaling even with 50 similar to 60% improvement on f(T) but strong dependence on finger number. The intrinsic noise extracted through lossy substrate de-embedding can consistently reflect the gain in fT and weak dependence on finger number. The NFmin at 10 GHz can be suppressed to 0.5dB for 65 nm nMOS corresponding to an optimized drain current, which is around 0.2 dB improvement over 80 nm devices. Noise suppression due to gate length scaling becomes even more significant in higher current region. The noise reduction is attributed to lower noise resistance (R-n) and real part of optimum source admittance (Re(Y-opt)). The accurate extraction of intrinsic noise provides useful guideline for RF CMOS device design and optimization in terms of speed, power, and noise.
A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
(2006)
Guo, J. C.
;
Tan, T. Y.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. EM simulation using ADS momentum is conducted to predict the on-chip inductor performance corresponding to wide range of substrate resistivities (rho(Si)=0.05 similar to 1K Omega-cm). Three operation modes such as TEM, slow-wave, and eddy current are reproduced. The model parameters manifest themselves physics-base through relevant correlation with rho(Si) over three operation modes. The onset of slow-wave mode can be consistently explained by a key element (R-P) introduced in our model, which accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate optimization design of on-chip inductors through physics-based model parameters relevant to varying substrate resistivities.
A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
(2006-01-01)
Guo, J. C.
;
Tan, T. Y.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. EAI simulation using ADS momentum is conducted to predict the on-chip inductor performance corresponding to wide range of substrate resistivities (rho(Si)=0.05 similar to 1K Omega-cm). Three operation modes such as TEM, slow-wave, and eddy current are reproduced. The model parameters manifest themselves physics-base through relevant correlation with psi over three operation modes. The onset of slow-wave mode can be consistently explained by a key element (R-p) introduced in our model, which accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate optimization design of on-chip inductors through physics-based model parameters relevant to varying substrate resistivities.
A scalable lossy substrate model for nanoscale RF MOSFET noise extraction and simulation adapted to various pad structures
(2007)
Guo, J. C.
;
Tsai, Y. H.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable lossy substrate model is developed and validated for nanoscale RF MOSFETs of different finger numbers and adopting various pad structures such as lossy, normal, and small pads. The broadband accuracy is justified by good match with S- and Y-parameters up to 40 GHz. The measured noise characteristics in terms of four noise parameters can be accurately simulated up to 18 GHz. The scalable lossy substrate model can consistently predict the abnormally strong ringer number dependence and nonlinear frequency response of noise figure (NF(min)) revealed by the devices with lossy pads. Furthermore, the scalable model can precisely distribute the substrate loss between the transmission line (TML) and pads of various metal topologies and the resulted excess noises. The enhanced model provides useful guideline for appropriate layout of pads and TML to effectivelv reduce the excess noises. The remarkably suppressed noise figure to ideally intrinsic performance can be approached by the small pad in this paper.
Broadband and scalable on-silicon-chip inductor model for varying substrate resistivities
(2006)
Guo, J. C.
;
Tan, T. Y.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. A key element (R(P)) introduced in our model can successfully accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate on-chip inductor design and optimization through physics-based model parameters relevant to lossy substrate.