Browsing by Author "Guo, JI"

Now showing 1 - 6 of 6

A memory efficient realization of cyclic convolution and its application to discrete cosine transform
(2003)
Chen, HC
;
Guo, JI
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and N-1/2 + 1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform
(2005-03-01)
Chen, HC
;
Guo, JI
;
Chang, TS
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition he content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or substractors, one small ROM module, a barrel shifter, and ((N - 1)/2) + 1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.
Distributed arithmetic realisation of cyclic convolution and its DFT application
(2005-12-01)
Chen, HC
;
Guo, JI
;
Jen, CW
;
Chang, TS
;
電子工程學系及電子研究所
The authors present a new hardware-efficient group distributed arithmetic (GDA) design approach for the one-dimensional (1-D) discrete Fourier transform (DFT). The approach adopts distributed arithmetic (DA) computation and exploits the good features of cyclic convolution to facilitate an efficient realisation of the 1-D N-point DFT using small ROM modules. a barrel shifter, and N accumulators. The proposed GDA design is achieved by rearranging the contents of the ROM into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DFT outputs to increase ROM utilisation. Moreover, combining the symmetrical property of the DFT coefficients with the proposed GDA design requires only half the ROM contents to be stored, which further reduces ROM size by a factor of two. Realisation of a long-length DFT formulated in cyclic convolution is based on data permutation of the rows and columns in the matrix to directly partition the long-length cyclic convolution into short ones, so that short length DFTs may be realised efficiently by the proposed GDA design to achieve low hardware cost. This design approach is termed the 'block-based group distributed arithmetic approach. Compared with existing systolic array designs and DA-based designs. the proposed GDA design can reduce the delay-area product by 29%-68% based on a 0.35 mu m CMOS cell library.
Fast perceptual convolution for room reverberation
(2003)
Lee, WC
;
Liu, CM
;
Yang, CH
;
Guo, JI
;
資訊工程學系
The FIR-based reverberators, which convolve the input sequence with an impulse response modelling the concert hall, have better quality compared to the IIR-based approach. However, the high computational complexity of the FIR-based reverberators limits the applicability to most cost-oriented system. This paper introduces a method that uses perceptual criterion to reduce the complexity of convolution methods for reverberation. Also, an objective measurement criterion is introduced to check the perceptual difference from the reduction. The result has shown that the length of impulse response can be cut off by 60% without affecting the perceptual reverberation quality. The method is well integrated into the existing FFT-based approach is have around 30% speed-up.
Hardware-efficient DFT designs with cyclic convolution and subexpression sharing
(2000-09-01)
Chang, TS
;
Guo, JI
;
Jen, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a hardware efficient design for the discrete Fourier transform (DFT), The proposed design not only applies the constant property, but also exploits the numerical property of the transform coefficients. DFT is first formulated as cyclic convolution form to make each DFT output sample computations have the same computation kernels. Then, by exploring the symmetries of DFT coefficients, the word-level hardware sharing can be applied, in which two times the throughput is obtained. Finally, bit-level common subexpression sharing can be efficiently applied to implement the complex constant multiplications by using only shift operations and additions. Though the three techniques have been proposed separately for transform, this paper integrates the above techniques and obtains additive improvements. The I/O channels in our design are limited to the two extreme ends of the architecture that results in low I/O bandwidth. Compared with the previous memory-based design, the presented approach can save 80% of gate area with two-times faster throughput for length N = 61. The presented approach can also be applied to power-of-two length DFT Similar efficient designs can be obtained for other transforms like DCT by applying the proposed approach.
The long length DHT design with a new hardware efficient distributed arithmetic approach and cyclic preserving partitioning
(2005-05-01)
Chen, HC
;
Chang, TS
;
Guo, JI
;
Jen, CW
;
電子工程學系及電子研究所
This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the tradeoff in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 mu m CMOS cell library.