Browsing by Author "Guo, Jiun-In"

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3D DEPTH MAP GENERATION FOR EMBEDDED STEREO APPLICATIONS
(2012)
Lee, Jui-Sheng
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Jian, Guo-An
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Chien, Cheng-An
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Chen, Peng-Sheng
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Guo, Jiun-In
This paper presents a low complexity 3D image depth map generation algorithm for embedded stereo applications. The proposed algorithm generates depth information based on a single view 2D image automatically. Owing to different scene characteristics of image, we propose a mechanism to classify images to "Scenery", "Normal" and "Close-up" types first and generate the associated depth map according to the proposed techniques. In addition, we propose a human detection method for strengthening the depth information in images with humans and post-processing for refining depth map. With good quality in the generated depth map, the proposed algorithm achieves about 93% in complexity reduction as compared to the traditional algorithm, which is suitable for realization in both the hardware and embedded systems for portable stereo applications.
A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
A 3D Hand Tracking Design for Gesture Control in Complex Environments
(2015)
Chien, Po-Yu
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Miao, Yuan-Hsiang
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Guo, Jiun-In
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a low-complexity design for 3D hand tracking, which can provide depth information and is able to work under critical backgrounds. This paper also proposes an effective way to segment hands out of entire image and also facilitates depth estimation of tracked hands in real-time by dual-camera systems. Multithreading and several techniques are applied to reduce computational complexity in proposed design. The final algorithm has been implemented both on PCs (with Intel Core i7 processor) and an embedded system (with ARM Cortex A9 processor). On PCs, it reaches 24 frames per second at VGA video. On the other hand, after reducing image size (i.e. QVGA video), it achieves the performance about 8 frames per second on PandaBoard embedded system.
A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications
(2018-01-01)
Chang, Shun-Min
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Tsai, Chia-Chi
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Guo, Jiun-In
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Blind Spot Detection (BSD) is an important technique for ADAS. We propose a BSD algorithm using Gabor filtering and optical flow to detect vehicles in the blind spot region for both day-time and night-time applications. For the day-time scene, the Gabor filtering is used to detect the vehicles, inside lane line, and outside lane line. After detection, the optical flow information calculated according to Horn-Schunck method is used to judge the motion of the vehicle candidates and filter the mistake-judgement. For the night-time scene, we try to find the head-light of the approaching cars. First, we perform binarization on the image first, find the center of gravity of the light-area, classify the light-area into 2 groups and judge it as a vehicle or not. The proposed BSD system achieves 93.58% recall and 95.83% precision in day time scene and 90.22% recall and 92.76% precision in night time scene. The algorithm can achieve performance of 89 fps on Intel Core I7 and 50 fps on Renesas R-Car M2 under 640x480 resolution.
A Forward Collision Avoidance System Adopting Multi-feature Vehicle Detection
(2014-01-01)
Chen, Guan-Yu
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Shen, Po-Chun
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Cho, Chao-Yi
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Vinay, M. S.
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Guo, Jiun-In
This paper presents a vehicle collision avoidance method and it is associated with the exploitation of multiple features based on the AdaBoost classifier result. The proposed system will enhance the precision rate and accuracy of vehicle detection from 72% to 96% using an AdaBoost detection method extracting multiple features in vehicle detection and false alarms are reduced.
A Low Complexity Multi-view Video Encoder Exploiting B-frame Characteristics
(2013)
Miao, Yuan-Hsiang
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Jian, Guo-An
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Wang, Li-Ching
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Lee, Jui-Sheng
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Guo, Jiun-In
This paper proposes a low complexity multi-view video encoder which includes mode decision and early termination based on B-frame characteristics. According to the statistics of coding mode distribution in different B-frame types, we classify all the coding modes into several classes and propose an early terminated mode decision algorithm that can largely reduce the computing complexity. On the other hand, MVD-based adaptive search range scheme is also included in the proposed encoding strategy. In our experimental results, the encoding time is saved up to 91%-93% but the quality loss is controlled within 0.1 dB PSNR drop.
A Low-Cost Scalable Voltage-Frequency Adjustor for Implementing Low-Power Systems
(2013)
Cheng, Ching-Hwa
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Hsu, Sheng-Wei
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Guo, Jiun-In
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The proposed low-cost, scalable, synthesizable Voltage-Frequency Adjustor (VFA) design provides voltage and frequency automatic adjustments for implementing low-power systems. This design is effective in reducing power consumption from managing the supplied current and clock frequency for the structurally dynamic varying systems. The VFA supplied electrical current amount and voltage level are automatically adjusted from sensing the voltage drop of the fanout load. This adjustment mechanism controls the activated power switch quantity to allow a structure varied design that can obtain a stable fanin voltage level, regardless of the designed module that is dynamically added or removed from the system. Compared to the conventional dynamic voltage frequency scaling technique, the VFA is cost effective and can be easily integrated with the target design as a single chip. The experimental results show that the combination of VFA chips and an H. 264 video decoder is successfully validated with 49%similar to 68% power reduction compared to the case that the H.264 video decoder directly uses an outer power supply.
A Multiple Vehicle Tracking and Counting Method and its Realization on an Embedded System with a Surveillance Camera
(2018-01-01)
Hsu, Yi-Hsuan
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Chang, Ssu-Yuan
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Guo, Jiun-In
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a tracking-by-detection method with a weighted scoring mechanism to associate the trackers and the detection results for accurate tracking and counting vehicles in a surveillance application. For the vehicle detection, the proposed method uses our robust PVA-lite deep learning model to detect vehicles. The experimental results show that the proposed method can achieve more than 95% in the average counting accuracy.
A Multiple-Lane Vehicle Tracking Method for Forward Collision Warning System Applications
(2017-01-01)
Li, Yuan-Fu
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Tsai, Chia-Chi
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Lai, Yi-Ting
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Guo, Jiun-In
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電子工程學系及電子研究所
This paper proposes a vehicle tracking method for the Forward Collision Warning System (FCWS). The proposed method applies vehicle detection and feature tracking to each frame in the videos to enhance the detection accuracy and increase the stability of vehicle localization. The proposed method can be applied to three-lane FCWS which includes left, main, and right lanes. The performance of the proposed three-lane FCWS can achieve 720x480 video@183 fps in average when realized in PC with Intel Core i7 processor with average detection accuracy of 94.05% at daytime and 86.90% at night. The proposed method is also implemented on Freescale i.MX6 embedded platform with a USB webcam to capture the video. Under the D1 (720x480) resolution, the performance of the proposed 3-lane FCWS can achieve 29 fps.
A Power-Aware Quad-Voltage H.264 Encoder Chip for Wireless Panoramic Endoscope Applications
(2015)
Xiao, An-Tia
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Yang, Shiang-Ren
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Miao, Yuan-Hsiang
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Cheng, Ching-Hwa
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Guo, Jiun-In
Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage ( HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.
A Real-time and Online Multiple-Type Object Tracking Method with Deep Features
(2019-01-01)
Hsu, Yi-Hsuan
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Guo, Jiun-In
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交大名義發表
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電子工程學系及電子研究所
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National Chiao Tung University
Object tracking is one of the most important things in intelligent vision system. Meanwhile, the most challenging issue in object tracking is how to keep the target's identity unchangeable with limited power consumption. In this paper, we propose a real-time and online tracking method to track multiple types of objects (e.g. pedestrian and car). Furthermore, to handle the ID switching problem, we provide a lightweight deep learning model which can recognize the similarity of objects. It can effectively solve the ID switching problem resulted from occlusion. Finally, we do some experiments to demonstrate that the proposed method achieves the state-of-the-art performance with less power consumption. The proposed method can solve the problem of high computation of tracking and keep the high accuracy of counting results with low ID switching rate. The experimental result shows that the average counting accuracy of the proposed method can reach more than 93% on pedestrian and vehicle counting applications. Also, it shows that the proposed method improves 68.2% on average of ID switching rate than previous works.
A REAL-TIME PARALLEL SCALABLE VIDEO ENCODER FOR MULTIMEDIA STREAMING SYSTEMS
(2013)
Jian, Guo-An
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Lee, Jui-Sheng
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Tan, Kheng-Joo
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Chen, Peng-Sheng
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Guo, Jiun-In
Scalable video coding (SVC) is a video coding technique that mainly aims its target in resolving problems of multimedia communication between servers and various clients with different computational power, transmission bandwidths, and display resolutions. In this paper, we developed a parallel SVC encoding system to achieve the real-time coding performance of SVC. First, a GOP-level bit-stream structure that is fully compatible with the standard SVC decoder was proposed to eliminate the data dependencies of encoding among GOPs. Based on this bit-stream structure, we developed a parallel SVC encoding algorithm to exploit the parallelism on multicore systems. Finally, the proposed parallel SVC encoder was implemented and integrated into a multimedia streaming system for the evaluation. The experimental results showed that for CIF/QCIF and VGA/QVGA 2-layer SVC encoding, the proposed parallel SVC encoder can achieve 50.96 and 103.99 times speedup with negligible PSNR drop, respectively.
A Single-Camera High Dynamic Range Technique by Using Contrast Enhancement and Exposure Control
(2014)
Li, Che-Cheng
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Hsu, Sheng-Wei
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Shen, Po-Chun
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Guo, Jiun-In
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電子工程學系及電子研究所
This paper presents a single-camera HDR imaging algorithm, which is able to solve all the extreme conditions by controlling the exposure time to get a well-exposed image and then enhancing it. The proposed system is divided into two parts, i.e. single-image HDR imaging technique and an exposure control method. The single-image HDR imaging technique integrates two methods, i.e. Dynamic Local Contrast Enhancement (DLCE) and fuzzy enhancement. The integrated result can handle both glaring region and dark region to exhibit good visibility for extreme conditions. In exposure control method, we utilize local average, camera response function and main object detection to achieve a well-exposed image. Finally, we implement our system on TI OMAP4430 embedded platform. The optimized program is able to achieve about 13 frames per second with VGA resolution.
A Smart Surveillance System with Multiple People Detection, Tracking, and Behavior Analysis
(2016)
Yang, Chia-Jui
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Chou, Ting
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Chang, Fong-An
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Chang Ssu-Yuan
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Guo, Jiun-In
This paper proposes an intelligence surveillance system in indoor environments, which support the functions of people detection, people tracking, and behavior analysis. Strong variation of lightness by switching lights and frequent crossing of people are two major design challenges of the proposed system, which will decrease the detection accuracy. Therefore, we propose a mechanism of updating background to react to the variation of lightness. Moreover, the ORB descriptor is added to be a unique feature of identifying people. It can make people tracking more precise during crossing. The proposed system is developed on PCs and implemented on embedded systems. On PCs with Intel i7@3.4GHz CPU running with a single core, we can reach the performance about D1 video at 22 fps. On an embedded system with ARM CortexA9@ 1.0GHz, we can achieve the performance about D1 video at 8 fps.
A Two level Mode Decision Algorithm for H.264 High Profile Intra Encoding
(2012)
Chang, Cheng-Yen
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Chien, Cheng-An
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Chang, Hsiu-Cheng
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Chen, Jia-Wei
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Guo, Jiun-In
A two level mode decision algorithm considering edge information for H.264 high profile intra encoding is proposed to reduce the computational complexity. In level one mode decision, the edge information is used to decide the appropriate intra coding block size according to the observations that a smooth macroblock usually chooses the large intra coding block size, and that a complex macroblock usually chooses the small one. In level two mode decision, we use the correlation between adjacent blocks to decide the appropriate prediction modes. The propose method achieves 34%similar to 59% reduction of computational complexity when compared to JM14 and the PSNR only drops 0.09 db in averag.
A Variable-Voltage Low-Power Technique for Digital Circuit System
(2016)
Xiao, An-Tai
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Miao, Yung-Siang
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Cheng, Ching-Hwa
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Guo, Jiun-In
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電子工程學系及電子研究所
A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H. 264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v similar to 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption.
A Verification-Aware Design Methodology for Thread Pipelining Parallelization
(2012-10-01)
Jian, Guo-An
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Chien, Cheng-An
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Chen, Peng-Sheng
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Guo, Jiun-In
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電子工程學系及電子研究所
This paper proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013-01-01)
Lee, Jui-Sheng
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Miao, Yuan-Hsiang
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Chien, Cheng-An
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Chang, Hsiu-Cheng
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Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
A VIEW SCALABLE MULTI-VIEW VIDEO DECODER SYSTEM
(2013)
Lee, Jui-Sheng
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Miao, Yuan-Hsiang
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Chien, Cheng-An
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Chang, Hsiu-Cheng
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Guo, Jiun-In
This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.
A Vision Radar System for Car Safety Driving Applications
(2017-01-01)
Tsai, Chia-Chi
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Lai, Yi-Ting
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Li, Yuan-Fu
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Guo, Jiun-In
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電子工程學系及電子研究所
This paper presents a vision radar system (VRS) integrating Lane Departure Warning System (LDWS) and Forward Collision Warning System (FCWS) for car safety driving applications. A dynamic threshold, which improves the accuracy of lane and vehicle detection in various weather conditions, and multiple frame approval, which conquers the effect of some tough scenes, are proposed. The designed radar-map facilitates warning message issuing of safety distance for forward and potential cutin vehicles. The proposed VRS can achieve 22 fps at 720x480 (D1) resolution on Freescale i.MX6 embedded platform.