Browsing by Author "Guo, Zi-Jing"

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A Java Processor IP Design for Embedded SoC
(2015-03-01)
Tsai, Chun-Jen
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Kuo, Han-Wen
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Lin, Zigang
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Guo, Zi-Jing
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Wang, Jun-Fu
In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform.
Stack Memory Design for a Low-cost Instruction Folding Java Processor
(2012)
Lin, Zi-Gang
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Kuo, Han-Wen
;
Guo, Zi-Jing
;
Tsai, Chun-Jen
;
資訊工程學系
In this paper, we propose the design of the stack memory for a low-cost Java processor that explores instruction-level parallelism. The Java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance Java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the Java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM; and is optimized for the Java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.