Browsing by Author "HSIAO, PY"

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A COMPARISON OF SIMILARITY MEASURES OF FUZZY VALUES
(1995-05-26)
CHEN, SM
;
YEH, MS
;
HSIAO, PY
;
交大名義發表
;
資訊工程學系
This paper extends the work of Pappis and Karacapilidis (1993) to present and compare the properties of several measures of similarity of fuzzy values. The measures examined in this paper are based on the geometric model, the set-theoretic approach, and the matching function S we presented in (Chen, 1988). It is shown that several properties are common to all measures and some properties do not hold for all of them.
A FUZZY CLUSTERING-ALGORITHM FOR GRAPH BISECTION
(1994-12-09)
YAN, JT
;
HSIAO, PY
;
交大名義發表
;
資訊工程學系
;
National Chiao Tung University
A fuzzy clustering algorithm based on global connection information is proposed to solve the graph bisection problem.
A FUZZY-NEURO APPROACH FOR TIMING-DRIVEN SYSTEM PARTITIONING IN VLSI MULTI-CHIP DESIGN
(1994)
CHANG, RI
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
A GENERAL SWITCHBOX ROUTER WITH VIA MINIMIZATION
(1993)
YAN, JT
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
A NEURAL-BASED PLACEMENT TECHNIQUE FOR RECTILINEAR APPLICATION
(1993)
CHANG, RI
;
CHANG, JC
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HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
A PARTITIONING-BASED APPROACH FOR THE ORIENTATION AND ROTATION ASSIGNMENTS OF MACRO CELLS
(1994)
YAN, JT
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
A ROBUST OVER-THE-CELL CHANNEL ROUTER
(1993-10-01)
CHANG, LD
;
HSIAO, PY
;
YAN, JT
;
SHEW, PW
;
資訊工程學系
In this paper, we present an efficient algorithm for over-the-cell routing in the standard cell layout design technology. Two variations are discussed: one aims to minimize the channel density with fewest tracks over the cells while the other aims to minimize the final channel width. Our algorithm can fit both the two-layer and three-layer routing models. With the two-layer model, there is a single routing layer over the cells for intercell connections. While with the three-layer model, there are two disjoint routing layers over the cells for intercell connections. In our approach, we decompose the problem into two phases: (1) over-the-cell routing and (2) conventional channel routing. The over-the-cell routing phase, which is executed iteratively, consists of two steps, routing over the cells and choosing net segments within the channel. For each iteration in the over-the-cell routing phase, our algorithm removes a net or a subnet which intersects the column with highest column density and route it over the cells according to some prioritized criteria. In comparison with the previous researches, our approach achieved the best effectiveness and has used the least CPU-time. On the average, the execution speed of our router is 163 and 4163 times faster than that of [8] and [9], respectively. Besides, our algorithm can produce results comparable to those produced by the WISER algorithm [10].
AN OPTIMAL ALGORITHM ON MINIMUM RECTANGULAR PARTITION OF VLSI LAYOUT
(1993)
YAN, JT
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
ARBITRARILY SHAPED CELL PLACEMENT BY 3-LAYER SELF-ORGANIZING NEURAL NETWORKS
(1994)
CHANG, RI
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
ARTIFICIAL TEXTURE GENERATION USING FORCE DIRECTED SELF-ORGANIZING MAPS
(1994)
CHANG, RI
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
CIRCUIT PLACEMENT IN ARBITRARILY-SHAPED REGIONS USING NEURAL-NETWORK
(1993)
CHANG, RI
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
DESIGNING A COMPLEMENTARY DESIGN RULE CHECKER BASED ON A BINARY BALANCED QUAD LIST QUAD TREE
(1992-07-01)
HSIAO, PY
;
YAN, JT
;
交大名義發表
;
資訊工程學系
;
National Chiao Tung University
An efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interative phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked only once either during the interactive or batch phase. This system and the embedded layout editor are designed on the basis of the binary balanced quad list quad tree (BBQLQT) and its region query functions. The BBQLQT is more efficient than the most recently published spatial data structure, the Weyten's quad list quad tree. One day, provided that the BBQLQT has being further improved, the performance of our system will be promoted without giving more additional design effort. This system is therefore proven to be fully modularised and independent of any of the other spatial data structures.
EFFICIENT HEIGHT REDUCTION OVER-THE-CELL CHANNEL ROUTER
(1995-07-01)
SHEW, PW
;
HSIAO, PY
;
LIM, YC
;
資訊工程學系
;
Department of Computer Science
The authors present a new algorithm for both two-layer and three-layer over-the-cell channel routing in the standard cell VLSI design. The approach exploits vacant terminals on the channel boundary effectively. It considers the following factors simultaneously to select net segments for routing over the cells: density distribution in the channel, the longest path in the vertical constraint graph, elimination of cycles in the vertical constraint graph and reduction in maximum cliques in the horizontal constraint graph. With respect to the PRIMARY 1 benchmark examples, the router achieved a 41.3% improvement over the Greedy channel router (one without using over-the-cell area) for a two-layer routing model and a 61.0% improvement for a three-layer routing model. This outperforms all previous algorithms.
EXPERT COMPACTOR - A KNOWLEDGE-BASED APPLICATION IN VLSI LAYOUT COMPACTION
(1991-01-01)
HSIAO, PY
;
TSAI, CC
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資訊工程學系
;
Department of Computer Science
A new application of artificial intelligence techniques in automatic compaction design for a VLSI mask layout is presented. To overcome the shortcomings of iterative search through a large problem space within a working memory, and therefore, to speed up the runtime of compaction, a set of rule-based region query operations and knowledge-based techniques for the plane sweep method are presented in this system. Experimental results have explored the possibility of using expert system technology to automate the compaction process by reasoning about the layout design, applying the sophisticated expert rules to its knowledge base.
FORCE DIRECTED SELF-ORGANZING MAPS FOR L-SHAPED CELL PLACEMENT USING DELTA LEARNING RULE
(1994)
CHANG, RI
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
GENETIC ALGORITHMS FOR THE MODULE ORIENTATION PROBLEM
(1994-07-21)
CHANG, RI
;
HSIAO, PY
;
交大名義發表
;
資訊工程學系
;
National Chiao Tung University
To solve the module orientation problem the optimal number of flips of modules needs to be determined so as to minimise total wire length. A genetic-based module orientation method is proposed. Experiments show that the proposed method performs better than the best method known for this problem.
NEW ITERATIVE CONSTRUCTION APPROACH TO ROUTING WITH COMPACTED AREA
(1991-01-01)
TSAI, CC
;
CHEN, SJ
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HSIAO, PY
;
FENG, WS
;
資訊工程學系
The new iterative construction approach presented in this paper consists of three algorithms, namely, channel expansion routing, track assignment, and module location refinement. These algorithms, contrary to the conventional methods implemented with a sequence of tools separately, are linked with a common data structure which guarantees a maximal compatibility. With an initial nonoverlapping placement as input, the iterative construction approach generates a final layout with more compacted area than the layout result from the one-dimensional compactor or some of two-dimensional compactors. Several layout examples in the literature are tested to show the effectiveness of our approach.
OPTIMAL TILE PARTITION FOR SPACE REGION OF INTEGRATED-CIRCUITS GEOMETRY
(1993-05-01)
HSIAO, PY
;
LIN, CY
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SHEW, PW
;
資訊工程學系
;
Department of Computer Science
An optimal tile partition (OTP) is presented for partitioning the space region of a VLSI layout plane into rectangular space tiles. It modifies the corner stitching data structure to optimise the space tile partition. There is a serious restriction in the original corner stitching data structure, i.e. the solid rectangles cannot overlap each other, whereas our OTP allows overlapping. This paper also shows three theorems with rigorous proofs and experimental results to obtain the minimal number of the space tiles through the OTP. Moreover, a dynamic plane-sweep algorithm based on region query for the OTP has been developed. Using the OTP, the memory efficiency and the local query operations of the original corner stitching data structure have been enhanced.
ORIENTATION ASSIGNMENT OF STANDARD CELLS USING A FUZZY MATHEMATICAL TRANSFORMATION
(1994)
YAN, JT
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
ORIENTATION ASSIGNMENT OF STANDARD CELLS USING A FUZZY MATHEMATICAL TRANSFORMATION
(1995-03-01)
YAN, JT
;
HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
It is well known that minimising total wire length reduces routing area in a standard cell layout. After the placement phase, another advanced improvement on total wire length is made by assigning the orientations of standard cells. In the paper, based on fuzzy c-means clustering, the authors develop two-way constrained fuzzy graph clustering and the transformation between the orientation assignment of standard cells and the constrained graph bisection to minimise total wire length. Finally, the proposed algorithm has tested several standard cell layouts, and the experimental results show that the proposed algorithm produces significant wire reduction on total wire length.