Browsing by Author "HSIEH, PW"

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AN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONS
(1993-08-01)
HSIEH, PW
;
TSAI, JM
;
LEE, CY
;
電控工程研究所
;
Institute of Electrical and Control Engineering
An area efficient IC for high-throughput median filtering applications is presented in this paper. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, we first map the algorithm onto a regular PE structure, where each PE consistis of shift register, comparator, and some control gates. Then we conduct full-custom circuit/layout design of the PE to meet performance requirement. A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 mum CMOS double metal technology. Two outstanding features of this IC are: (1) any specified order of input patterns can be produced within one clock cycle; (2) each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus this IC releases the bottle-neck of median search in hardware realization for many system designs, making real-time performance achievable.
HIGH-SPEED MEDIAN FILTER DESIGNS USING SHIFTABLE CONTENT-ADDRESSABLE MEMORY
(1994-12-01)
LEE, CY
;
HSIEH, PW
;
TSAI, JM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many image/video applications, The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs, To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture, The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells- sort-cell and compare-cell, Thus the design becomes very regular, More specifically any specified order can be obtained within one cycle and a high-speed clock rate can be achieved, A proto-type chip for 64 samples based on this architecture has been implemented and tested, Results show that a clock rate up to 50 MHz can be achieved using a 1.2 mu m CMOS double metal technology.