Browsing by Author "HSU, CC"

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A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS
(1994-01-01)
HUANG, HS
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CHANG, CY
;
CHEN, KL
;
LIU, IO
;
HSU, CC
The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS) protection circuits are presented. Bilateral latch-up self-triggering resulting from serial resistance or serial inductance on V-dd or V-ss is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The studies on the behavior of bilateral latch-up in CMOS protection circuits are increasingly important since low-power applications are the future trend.
ANALYSIS OF BILATERAL LATCH-UP TRIGGERING IN VLSI CIRCUITS
(1994-02-01)
HUANG, HS
;
CHANG, CY
;
HSU, CC
;
CHEN, KL
;
LIN, JK
COMPLEX-SURFACE MODELING WITH BIAS AND TENSION
(1991-04-01)
CHEN, DP
;
LIN, TL
;
HSU, CC
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交大名義發表
;
機械工程學系
The concept of applying bias and tension to cubic-spline curves for shape adjustment has been discussed in many papers in the literature, but few of them have mentioned any practical use of the parameter-controlled curves in surface modelling or mechanical-component design. In the paper, the influence of bias and tension on the shaping of the conventional cubic spline is investigated, and the tested values of the parameters are used in the surface models of various machine parts.
DISTRIBUTED TASK ASSIGNMENT USING CRITICAL PATH ESTIMATE
(1993-11-01)
HSU, CC
;
LEE, PJ
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資訊科學與工程研究所
;
Institute of Computer Science and Engineering
A very general task assignment scheme for a distributed computing system is presented in this paper. It takes execution time, communication time, and idle time into consideration. All possible task assignments are formed as a state space tree where a path from the root node of the tree to a node represents a partial or total task assignment. We propose an approach called the critical path overestimate for achieving a suboptimal task assignment and pruning most of the nodes of the tree. Combining the above approach with a divide-and-conquer method, we can further reduce the complexity of the problem, and therefore attain a satisfactory solution. Results from a wide range of experiments reveal that the proposed approaches perform well because of their giving close approximation to the actual cost and saving a high percentage of node generations.
THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS
(1993-11-01)
HUANG, HS
;
CHANG, CY
;
HSU, CC
;
CHEN, KL
;
LIN, JK
A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfull explains this phenomenon.