Browsing by Author "HSU, CCH"

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ANOMALOUS REVERSE SHORT-CHANNEL EFFECT IN P+ POLYSILICON GATED P-CHANNEL MOSFET
(1994-11-01)
CHANG, CY
;
LIN, CY
;
CHOU, JW
;
HSU, CCH
;
PAN, HT
The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p+ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF2 doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator.
DIRECT OBSERVATION OF CHANNEL-DOPING-DEPENDENT REVERSE SHORT-CHANNEL EFFECT USING DECOUPLED C-V TECHNIQUE
(1994-01-01)
GUO, JC
;
HSU, CCH
;
CHUNG, SSS
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A non-destructive high resolution ''Decoupled C-V Technique'' for small geometry devices has been developed and demonstrated to successfully extract the intrinsic channel capacitance of submicron metal-oxide-semiconductor field effect transistors (MOSFET's). The effective channel doping concentration calculated from the extracted intrinsic gate capacitance presents an obvious dopant concentration enhancement in the intrinsic channel region of submicron devices compared to that of long channel devices, as the channel implant dose increases beyond a critical value. The anomalous reverse short channel effect i.e. threshold voltage increases with channel length scaled down, is simultaneously observed on the heavily doped short channel devices. The self-consistency between the C-V and I-V measurement supports that the reverse short channel effect apparent in the submicron CMOS technology is due to the channel dopant enhancement induced by high dose channel implants for both N-channel and P-channel devices.
SUPPRESSION OF BORON PENETRATION IN BF2-IMPLANTED P-TYPE GATE MOSFET BY TRAPPING OF FLUORINES IN AMORPHOUS GATE
(1995-08-01)
LIN, CY
;
CHANG, CY
;
HSU, CCH
;
電控工程研究所
;
奈米中心
This work reports the use of amorphous/polysilicon gate electrode in BF2-implanted poly-gated P-MOSFET's to suppress the boron penetration, SIMS analysis clearly illustrates that fluorine prefers to accumulate in the layer of amorphous silicon. The retardation of boron diffusion is therefore achieved by the trapping of fluorine in the amorphous layer of stacked amorphous/polysilicon (SAP) p-type gate due to a lower diffusion rate of fluorine in the amorphous silicon layer. Polysilicon depletion effect did not become more severe by introducing the amorphous silicon. In addition, gate oxide reliability is not degraded by using this gate structure. Results show that the structure is a promising gate electrode for future dual-poly gate CMOS technology development.
TRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFET
(1995-02-01)
GUO, JC
;
CHANG, MC
;
LU, CY
;
HSU, CCH
;
CHUNG, SSS
For the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5 x 10(16) similar to 5 x 10(17) cm(-3)), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics.