Browsing by Author "HSU, SL"

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DIRECT EVIDENCE OF GATE OXIDE THICKNESS INCREASE IN TUNGSTEN POLYCIDE PROCESSES
(1991-11-01)
HSU, SL
;
LIU, LM
;
LIN, MS
;
CHANG, CY
;
電子工程學系及電子研究所
The increase of the "effective" gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and annealed W polycide are analyzed by secondary ion mass spectrometry, transmission electron microscopy (TEM), and high-frequency CV measurements. The TEM cross section shows that the gate oxide thicknesses are approximately 244 and approximately 285 angstrom for as-deposited and 1000-degrees-C annealed samples, respectively. The TEM results agree with that from CV measurements. The TEM analyses provide a direct physical evidence of an additional oxide thickness (approximately 41 angstrom) during the W-polycide annealing.
FIELD INVERSION GENERATED IN THE CMOS DOUBLE-METAL PROCESS DUE TO PETEOS AND SOG INTERACTIONS
(1993-01-01)
HSU, SL
;
LIU, LM
;
FANG, CH
;
YING, SL
;
CHEN, TL
Severe field inversion has been observed in the circuits fabricated by the CMOS double metal process using PETEOS/inorganic SOG/PEOX as the inter-metal dielectrics and PEOX/PECVD nitride as the passivation layer. We have performed detailed studies to conclude that the field inversion is caused by the interaction between PETEOS and non-carbon-based SOG, triggered by the H+ released from PECVD nitride during the sintering. No field inversion is observed when PEOX/inorganic SOG/PEOX is used as the inter-metal dielectrics. The effect of field inversion on the circuit yield is also discussed.