Browsing by Author "HUANG, HS"

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A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS
(1994-01-01)
HUANG, HS
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CHANG, CY
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CHEN, KL
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LIU, IO
;
HSU, CC
The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS) protection circuits are presented. Bilateral latch-up self-triggering resulting from serial resistance or serial inductance on V-dd or V-ss is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The studies on the behavior of bilateral latch-up in CMOS protection circuits are increasingly important since low-power applications are the future trend.
ANALYSIS OF BILATERAL LATCH-UP TRIGGERING IN VLSI CIRCUITS
(1994-02-01)
HUANG, HS
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CHANG, CY
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HSU, CC
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CHEN, KL
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LIN, JK
CHARGE LOSS DUE TO AC PROGRAM DISTURBANCE STRESSES IN EPROMS
(1993-09-01)
LIN, JK
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CHANG, CY
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WANG, TH
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HUANG, HS
;
CHEN, KL
Charge loss in interpolyoxide erasable programmable read-only memories (EPROMs) due to program disturbance by alternating current pulses applied to the drain was studied for the first time. It was found that the charge loss due to ac stress is more severe than that due to dc stress. Experimental results reveal that the more positive the floating gate potential, the more severe is the drain ac disturbance observed. The main reason for the charge loss is the displacement current which agitates the charges in the floating gate, creating a leakage path from the floating gate to the drain, in which the drain-to-floating-gate overlapping capacitance C(fd) plays an important role. The drain dc stresses of interpolyoxide/nitride/oxide (ONO) EPROMs were also measured under different bias conditions and temperatures. The data show that higher dc electric field of the floating gate to the drain results in larger V(th) shift, which can be accelerated by elevated temperature. In addition, the control gate ac stress-enhanced drain dc disturbance was also measured. We proposed that the dc drain stress is applied during the ac gate stress, which results in a heating effect. The results support the concept of dielectric ac heating.
NEW POLYSILICON-OXIDE-NITRIDE-OXIDE-SILICON ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY DEVICE APPROACH FOR ELIMINATING OFF-CELL LEAKAGE CURRENT
(1994-05-01)
LIN, JK
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CHANG, CY
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HUANG, HS
;
CHEN, KL
;
KUO, DC
A new polysilicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory (EEPROM) device, which eliminated off-cell leakage current, has been described and fabricated. The leakage current is easily encountered in metal-nitride-oxide-silicon (MNOS)-type EEPROMs. Two parasitic transistors, which are in parallel with the desired variable V(t) cell, are responsible for the leakage current. We demonstrated that the parasitic transistors are caused either by the nearly constant-threshold-voltage parasitic transistors surrounding the active region or by the ''fringing effect'' in poly-Si gate edges. The on-state and off-state I-V curves of the cell are shown and compared with those of two other different devices. The results reveal that the off-cell leakage current, which is observed in the other two devices, is completely eliminated in the proposed cell.
THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS
(1993-11-01)
HUANG, HS
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CHANG, CY
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HSU, CC
;
CHEN, KL
;
LIN, JK
A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfull explains this phenomenon.
TRANSIENT AND STEADY-STATE CARRIER TRANSPORT UNDER HIGH-FIELD STRESSES IN SONOS EEPROM DEVICE
(1993-06-01)
LIN, JK
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CHANG, CY
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HUANG, HS
;
HO, TS
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CHEN, KL
The carrier transport model of tunneling oxide in a polysilicon-oxide-nitride-oxide-silicon (SONOS) device has been developed. The model is deduced from WKB approximation, and uses Fermi-Dirac statistics. Using the J-E and accompanied by Arnett's trapping model, the switching behavior of the SONOS device can be predicted in a very wide range of switching times from 1 mus to 0.1 s. The steady-state charge distribution and electric field in Si3N4 are also calculated. From Arnett's fundamental equations of Si3N4, we deduce the steady-state equations which describe the electric field and trapping charges. The trapping parameters and detrapping factor v are discussed and the results are obtained via computer for different temperatures and stress voltages, which are based on the current measurement of SONOS devices. We find that the detrapping effect is somewhat less dominant compared to the trapping effect in our simulations.