Browsing by Author "HUANG, HY"

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ATMOSPHERIC AEROSOL SAMPLING BY AN ANNULAR DENUDER SYSTEM AND A HIGH-VOLUME PM(10) SAMPLER
(1995)
TSAI, CJ
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HUANG, HY
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交大名義發表
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環境工程研究所
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National Chiao Tung University
An Annular Denuder System (ADS) was used to study sampling errors of total PM(10) and soluble ionic species concentrations determined by the high volume PM(10) (HVPM(10)) sampler. Experimental results show that in the HVPM(10) sampler, more alkaline glass fiber filters collect more sulfate and nitrate but less ammonium ion than quartz filters. However, total PM(10) concentrations do not seem to depend on the types of filters. Artifact sulfate concentrations in glass fiber filters of the HVPM(10) sampler are found to exceed those predicted by the Coutant's model. It is suggested that artifact sulfate and nitrate not only occur within filters but also in particle deposits. Chloride ion concentrations in the filters of the HVPM(10) sampler are underestimated significantly due to evaporative loss of ammonium chloride.
DESIGN AND APPLICATION OF PIPELINED DYNAMIC CMOS TERNARY LOGIC AND SIMPLE TERNARY DIFFERENTIAL LOGIC
(1993-08-01)
WU, CY
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HUANG, HY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
New dynamic CMOS ternary logic circuits, which can be used to form a pipelined system with the nonoverlapped two-phase clocks, are proposed and investigated. All the proposed new dynamic ternary gates do not have dc power dissipations and have full voltage swings. For complex ternary logic, a new circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed. The design procedure of the STDL is developed for the optimal implementation. An experimental chip has been fabricated in 1.2-mum CMOS process and tested, which successfully verifies part of the logic functions of the proposed new dynamic ternary logic. A new binary pipelined multiplier is designed by using the proposed dynamic ternary logic circuits in the interior of the multiplier in the coding of radix-2 redundant positive-digit number. The new structure has the advantages of higher operating frequency as well as much less latency and total device count as compared with the conventional binary parallel pipelined multiplier. It has been shown that all the developed dynamic ternary logic circuits have certain advantages in speed, power dissipation, chip area, and clock complexity over other dynamic ternary logic circuits. Moreover, the pipelined structure is free from race problems.
NEW DESIGN METHODOLOGY AND NEW DIFFERENTIAL LOGIC-CIRCUITS FOR THE IMPLEMENTATION OF TERNARY LOGIC SYSTEMS IN CMOS-VLSI WITHOUT PROCESS MODIFICATION
(1994-06-01)
HUANG, HY
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WU, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new design methodology is proposed and analyzed for the design of ternary logic systems. In the new ternary logic systems, no conversions among radices are required and only the two-state ternary literals associated with the ternary signals are transmitted in the whole system. With the new design methodology, the ternary systems can be realized by the dynamic CMOS logic circuits which are simple and fully compatible with those of the conventional binary logic circuits in process, power supply, and logic levels. A new dynamic differential logic called the CMOS Redundant Differential Logic (CRDL) is also developed to increase the logic flexibility and the circuit performance. Using the new design methodology and the CRDL circuits, the multiplier with redundant binary addition tree is designed in both non-pipelined and pipelined systems. The experimental chip has been fabricated and measured, which successfully verifies the correctness of the logic functions and the speed performance of the designed circuits.