Browsing by Author "HWANG, JH"

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ALGAAS/GAAS HETEROJUNCTION BIPOLAR-TRANSISTORS ON SI SUBSTRATE USING EPITAXIAL LIFT-OFF
(1995-09-01)
FAN, JC
;
LEE, CP
;
HWANG, JA
;
HWANG, JH
;
電子工程學系及電子研究所
Epitaxial lift-off (ELO) technique was used for the first time to transplant AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's) to Si substrates. Both preprocessed (devices processed before transplantation) and postprocessed (devices processed after transplantation) ELO HBT's On Si were demonstrated in this study. The characteristics of those HBT's on Si with either technique show nearly identical characteristics of the HBT's on GaAs without transplantation, indicating the film quality is maintained after transplantation. Devices with a high current gain of 550 were transplanted without any degradation, and the current gain is not limited by the ELO process. This current gain value is the highest reported for GaAs HBT's on Si with any techniques.
ALGAAS/GAAS HETEROJUNCTION BIPOLAR-TRANSISTORS ON SI SUBSTRATE USING EPITAXIAL LIFT-OFF
(1995-09-01)
FAN, JC
;
LEE, CP
;
HWANG, JA
;
HWANG, JH
;
電子工程學系及電子研究所
Epitaxial lift-off (ELO) technique was used for the first time to transplant AlGaAs/GaAs Heterojunction Bipolar Transistors (HBT's) to Si substrates. Both preprocessed (devices processed before transplantation) and postprocessed (devices processed after transplantation) ELO HBT's On Si were demonstrated in this study. The characteristics of those HBT's on Si with either technique show nearly identical characteristics of the HBT's on GaAs without transplantation, indicating the film quality is maintained after transplantation. Devices with a high current gain of 550 were transplanted without any degradation, and the current gain is not limited by the ELO process. This current gain value is the highest reported for GaAs HBT's on Si with any techniques.
REACTIVE ION ETCH OF GAAS AND ALGAAS USING BCL3, SICL4 AND SF6, INSTEAD OF CCL2F2
(1994)
WU, JW
;
CHANG, CY
;
LIN, KC
;
CHANG, EY
;
HWANG, JH
SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHING
(1995-08-01)
CHANG, SF
;
HWANG, JH
;
JEN, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Block matching is a widely used motion estimation algorithm in current video systems, Among typical searching strategies, the full search scheme provides better precision and regular data flow as well as higher parallelism, a characteristic that is advantageous for VLSI implementation, However, the huge computation load incurred by full search results in high cost, especially in high pixel rate applications, Since block matching algorithm is used in a wide range of pixel rates, an architecture that is cascadable and offers variable computing power is promising, In the first part of this paper, an approach based on dependence graph (DG) is proposed to analyze the operation sequence and data flow of full search block matching. The approach employs a transformation on DG's, called slice and tile, to produce different forms of DG's, Through this technique, most existing architectures can be represented in graphs for analysis, and new architectures can be found, In the second part of this paper, a new architecture is presented that features cascadable modules of processing elements (PE's) with simple interconnection. Therefore, flexibility in computing power is available. The other advantages include variable sizes of the search area and 100% PE utilization, These characteristics offer great flexibility and efficiency for different applications. This architecture is implemented with thirty-two PE's in one chip that consists of 102 K transistors.