Browsing by Author "Han, Ping-Cheng"

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Halbleitervorrichtung und Verfahren zur Herstellung derselben
(2018-06-21)
CHANG EDWARD YI
;
LIU SHIH-CHIEN
;
HUANG CHUNG-KAI
;
WU CHIA-HSUN
;
HAN PING-CHENG
A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.
High Performance Normally-Off AlGaN/GaN MIS-HEMT Using Charge Storage Technique
(2019-01-01)
Han, Ping-Cheng
;
Yang, Chih-Yi
;
Lee, Ming-Wen
;
Wu, Jui-Sheng
;
Wu, Chia-Hsun
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Quang Ho Luc
;
Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
Normally-Off Tri-Gate GaN MIS-HEMTs with 0.76 m Omega center dot cm(2) Specific On-Resistance for Power Device Applications
(2019-08-01)
Wu, Chia-Hsun
;
Chen, Jian-You
;
Han, Ping-Cheng
;
Lee, Ming-Wen
;
Yang, Kun-Sheng
A GaN metal-insulator-semiconductor high electronmobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge-trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V-th) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R-ON) and high positive V-th. The designed tri-gate device exhibits a high V-th of +2.61 V at current density (I-DS) = 1 mu A/mm, a high maximum current density (I-DS, MAX) of 896 mA/mm, a low R-ON of 5.0 Omega center dot mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R-ON,R- SP) among reported normallyoff GaN device results with BV > 650 V.
Recess-Free Normally-off GaN MIS-HEMT Fabricated on Ultra-Thin-Barrier AlGaN/GaN Heterostructure
(2019-01-01)
Han, Ping-Cheng
;
Wu, Chia-Hsun
;
Ho, Yu-Hsuan
;
Yan, Zong-Zheng
;
Chang, Edward Yi
In this work, a recess-free thin AlGaN barrier metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) with high threshold voltage of 3.19V, high maximum drain current of 716 mA/mm and high breakdown voltage of 906V is demonstrated for the first time. Three different thin barrier structures were compared for device performance. In addition, long-term reliability measurements were carried out to investigate the interface quality of the devices with and without gate recess. The recessfree device exhibits a smaller Vth hysteresis and a more stable performance than those of gate recessed devices. Overall, the recess-free thin barrier AlGaN/GaN MIS-HEMT demonstrates promising performance for power switching applications.
Study of Charge Trapping Effects on AlGaN/GaN HEMTs Under UV Illumination With Pulsed I-V Measurement
(2020-06-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Chen, Bo-Yuan
;
Huang, Guo-Wei
;
Chuang, Chia-Wei
The charge trapping effects on AlGaN/GaN HEMTs under UV illumination are investigated using the pulsed current-voltage (I-V) measurement method. The test samples are unpassivated Schottky-gate HEMTs and metal-insulator-semiconductor HEMTs (MIS-HEMTs) with SiN gate dielectric. For HEMTs, the dominant charge trapping sources are the surface trap states, whereas, for MIS-HEMTs, they are trap states in the SiN gate dielectric and GaN buffer. When these devices are shined with the UV light, the drain current increases apparently in both samples owing to the generated photocurrent. By combining the UV illumination and pulsed I-V measurement, we find out the UV light has less effect on the surface charge trapping in the unpassivated HEMTs. Moreover, in MIS-HEMTs, we observe the charge trapping in the SiN gate dielectric becomes more serious under UV illumination, whereas the charge trapping in the GaN buffer is suppressed significantly. These findings are important for designing a GaN-based HEMT for photonic applications. In addition, the different responses of the surface-, buffer-, and gate-dielectric-related charge trapping to the UV light suggest that it would be easier to distinguish the trap types by introducing the UV illumination during the pulse measurement.