Browsing by Author "Hariharan, R. M."

Now showing 1 - 2 of 2

Hetero structure PNPN tunnel FET: Analysis of scaling effects on counter doping
(2018-08-15)
Joseph, H. Bijo
;
Singh, Sankalp Kumar
;
Hariharan, R. M.
;
Priya, P. Aruna
;
Kumar, N. Mohan
This paper investigates the effect of counter doping in an n-Tunneling Field Effect Transistor(nTFET). Effect of various pocket lengths between the source and the channel was investigated. A double gate structure with a 2 nm counter doped pocket provides higher rate of band-to-band tunneling and better on current, thereby increasing the device performance. Steep Subthreshold Swing (SS) of around 23 mV/dec was obtained due to larger band bending at a low operating voltage of 0.5 V. The low leakage current greatly reduces power consumption. The degree of depletion in pocket with smaller dimensions enhances device performance by achieving good electrical characteristics in both above and below threshold regimes. Increase in pocket length degrades the device performance thus affecting the subthreshold swing. (C) 2018 Elsevier B.V. All rights reserved.
Simulation study of gated nanowire InAs/Si Hetero p channel TFET and effects of interface trap
(2019-11-15)
Joseph, H. Bijo
;
Singh, Sankalp Kumar
;
Hariharan, R. M.
;
Tarauni, Yusuf
;
Thiruvadigal, D. John
The impact of EOT (Equivalent Oxide Thickness) scaling, diameter scaling, and interface traps on the performance of gated InAs/Si Hetero pTFET (Tunneling field effect transistor) is investigated. EOT scaling improves SS (SubthresholdSwing) below the thermal limit and on current moderately. Diameter scaling decreases on current and marginally improves SS. The simulation study validates that the transfer characteristics of pTFET in sub-threshold region are completely dominated by thermionic emission of holes and TAT (Trap Assisted Tunneling). This in turn blocks SS to attain < 60 mV/dec. Furthermore, Si/Oxide interface traps minimize the electrostatic gate coupling with channel region additionally deteriorates SS. Interface trap density with different values denotes that sub 2.3k(B)T/q SS can only be realized for interface trap densities D-it < 1 x 10(11) cm(-2)eV(-1) at both InAs/Si and Si/Oxide. Hence this reaffirms the experimental data, that the prerequisite of D-it < 1 x 10(12) cm(-2)eV(-1) for InAs/Si nanowire p-TFET.